21 Search Results for "Vardanega, Tullio"

Volume

OASIcs, Volume 23

12th International Workshop on Worst-Case Execution Time Analysis

WCET 2012, July 10, 2012, Pisa, Italy

Editors: Tullio Vardanega

Document
DOI: 10.4230/OASIcs.WCET.2016.1
Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis

Authors: Enrique Díaz, Jaume Abella, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-Askasua, Tullio Vardanega, and Francisco J. Cazorla

Published in: OASIcs, Volume 55, 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)

Abstract
Measurement-based timing analysis (MBTA) is often used to determine the timing behaviour of software programs embedded in safety-aware real-time systems deployed in various industrial domains including automotive and railway. MBTA methods rely on some form of instrumentation, either at hardware or software level, of the target program or fragments thereof to collect execution-time measurement data. A known drawback of software-level instrumentation is that instrumentation itself does affect the timing and functional behaviour of a program, resulting in the so-called probe effect: leaving the instrumentation code in the final executable can negatively affect average performance and could not be even admissible under stringent industrial qualification and certification standards; removing it before operation jeopardizes the results of timing analysis as the WCET estimates on the instrumented version of the program cannot be valid any more due, for example, to the timing effects incurred by different cache alignments. In this paper, we present a novel approach to mitigate the impact of instrumentation code on cache behaviour by reducing the instrumentation overhead while at the same time preserving and consolidating the results of timing analysis.
Cite as

Enrique Díaz, Jaume Abella, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-Askasua, Tullio Vardanega, and Francisco J. Cazorla. Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 1:1-1:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)

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@InProceedings{diaz_et_al:OASIcs.WCET.2016.1,
  author =	{D{\'\i}az, Enrique and Abella, Jaume and Mezzetti, Enrico and Agirre, Irune and Azkarate-Askasua, Mikel and Vardanega, Tullio and Cazorla, Francisco J.},
  title =	{{Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{1:1--1:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.1},
  URN =		{urn:nbn:de:0030-drops-68946},
  doi =		{10.4230/OASIcs.WCET.2016.1},
  annote =	{Keywords: WCET, Measurements, Instrumentation overhead}
}
Document
DOI: 10.4230/OASIcs.WCET.2016.9
Measurement-Based Timing Analysis of the AURIX Caches

Authors: Leonidas Kosmidis, Davide Compagnin, David Morales, Enrico Mezzetti, Eduardo Quinones, Jaume Abella, Tullio Vardanega, and Francisco J. Cazorla

Published in: OASIcs, Volume 55, 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)

Abstract
Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has caused a large fraction of real-time systems industry to avoid using them, especially in the automotive sector. For measurement-based timing analysis (MBTA) - the dominant technique in domains such as automotive - cache challenges the definition of test scenarios stressful enough to produce (cache) layouts that causing high contention. In this paper, we present our experience in enabling the use of caches for a real automotive application running on an AURIX multiprocessor, using software randomization and measurement-based probabilistic timing analysis (MBPTA). Our results show that software randomization successfully exposes - in the experiments performed for timing analysis - cache related variability, in a manner that can be effectively captured by MBPTA.
Cite as

Leonidas Kosmidis, Davide Compagnin, David Morales, Enrico Mezzetti, Eduardo Quinones, Jaume Abella, Tullio Vardanega, and Francisco J. Cazorla. Measurement-Based Timing Analysis of the AURIX Caches. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 9:1-9:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)

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@InProceedings{kosmidis_et_al:OASIcs.WCET.2016.9,
  author =	{Kosmidis, Leonidas and Compagnin, Davide and Morales, David and Mezzetti, Enrico and Quinones, Eduardo and Abella, Jaume and Vardanega, Tullio and Cazorla, Francisco J.},
  title =	{{Measurement-Based Timing Analysis of the AURIX Caches}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{9:1--9:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.9},
  URN =		{urn:nbn:de:0030-drops-69028},
  doi =		{10.4230/OASIcs.WCET.2016.9},
  annote =	{Keywords: WCET, caches, AURIX, Automotive}
}
Document
DOI: 10.4230/OASIcs.WCET.2015.11
Software-enforced Interconnect Arbitration for COTS Multicores

Authors: Marco Ziccardi, Alessandro Cornaglia, Enrico Mezzetti, and Tullio Vardanega

Published in: OASIcs, Volume 47, 15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015)

Abstract
The advent of multicore processors complicates timing analysis owing to the need to account for the interference between cores accessing shared resources, which is not always easy to characterize in a safe and tight way. Solutions have been proposed that take two distinct but complementary directions: on the one hand, complex analysis techniques have been developed to provide safe and tight bounds to contention; on the other hand, sophisticated arbitration policies (hardware or software) have been proposed to limit or control inter-core interference. In this paper we propose a software-based TDMA-like arbitration of accesses to a shared interconnect (e.g. a bus) that prevents inter-core interference. A more flexible arbitration scheme is also proposed to reserve more bandwidth to selected cores while still avoiding contention. A proof-of-concept implementation on an AURIX TC277TU processor shows that our approach can apply to COTS processors, thus not relying on dedicated hardware arbiters, while introducing little overhead.
Cite as

Marco Ziccardi, Alessandro Cornaglia, Enrico Mezzetti, and Tullio Vardanega. Software-enforced Interconnect Arbitration for COTS Multicores. In 15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015). Open Access Series in Informatics (OASIcs), Volume 47, pp. 11-20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2015)

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@InProceedings{ziccardi_et_al:OASIcs.WCET.2015.11,
  author =	{Ziccardi, Marco and Cornaglia, Alessandro and Mezzetti, Enrico and Vardanega, Tullio},
  title =	{{Software-enforced Interconnect Arbitration for COTS Multicores}},
  booktitle =	{15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015)},
  pages =	{11--20},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-95-8},
  ISSN =	{2190-6807},
  year =	{2015},
  volume =	{47},
  editor =	{Cazorla, Francisco J.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2015.11},
  URN =		{urn:nbn:de:0030-drops-52526},
  doi =		{10.4230/OASIcs.WCET.2015.11},
  annote =	{Keywords: Multicore, Resource Arbitration, Interference, Mixed-Criticality}
}
Document
DOI: 10.4230/LITES-v002-i001-a001
Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems

Authors: Enrico Mezzetti, Marco Ziccardi, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, and Francisco J. Cazorla

Published in: LITES, Volume 2, Issue 1 (2015). Leibniz Transactions on Embedded Systems, Volume 2, Issue 1

Abstract
Cache randomization per se, and its viability for probabilistic timing analysis (PTA) of critical real-time systems, are receiving increasingly close attention from the scientific community and the industrial practitioners. In fact, the very notion of introducing randomness and probabilities in time-critical systems has caused strenuous debates owing to the apparent clash that this idea has with the strictly deterministic view traditionally held for those systems. A paper recently appeared in LITES (Reineke, J. (2014). Randomized Caches Considered Harmful in Hard Real-Time Systems. LITES, 1(1), 03:1-03:13.) provides a critical analysis of the weaknesses and risks entailed in using randomized caches in hard real-time systems. In order to provide the interested reader with a fuller, balanced appreciation of the subject matter, a critical analysis of the benefits brought about by that innovation should be provided also. This short paper addresses that need by revisiting the array of issues addressed in the cited work, in the light of the latest advances to the relevant state of the art. Accordingly, we show that the potential benefits of randomized caches do offset their limitations, causing them to be - when used in conjunction with PTA - a serious competitor to conventional designs.
Cite as

Enrico Mezzetti, Marco Ziccardi, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, and Francisco J. Cazorla. Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems. In LITES, Volume 2, Issue 1 (2015). Leibniz Transactions on Embedded Systems, Volume 2, Issue 1, pp. 01:1-01:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2015)

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@Article{mezzetti_et_al:LITES-v002-i001-a001,
  author =	{Mezzetti, Enrico and Ziccardi, Marco and Vardanega, Tullio and Abella, Jaume and Qui\~{n}ones, Eduardo and Cazorla, Francisco J.},
  title =	{{Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems}},
  journal =	{Leibniz Transactions on Embedded Systems},
  pages =	{01:1--01:10},
  ISSN =	{2199-2002},
  year =	{2015},
  volume =	{2},
  number =	{1},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/LITES-v002-i001-a001},
  doi =		{10.4230/LITES-v002-i001-a001},
  annote =	{Keywords: Real-time systems, Probabilistic WCET, Randomized caches}
}
Document
DOI: 10.4230/OASIcs.WCET.2014.31
Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art

Authors: Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Christine Rochange, Tullio Vardanega, and Francisco J. Cazorla

Published in: OASIcs, Volume 39, 14th International Workshop on Worst-Case Execution Time Analysis (2014)

Abstract
The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been accentuated with the arrival of multicore processors. From the state of the art on the subject, there appears to be considerable diversity in the understanding of the problem and in the "approach" to solve it. This sparseness makes it difficult for any reader to form a coherent picture of the problem and solution space. This paper draws a tentative taxonomy in which each known approach to the problem can be categorised based on its specific goals and assumptions.
Cite as

Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Christine Rochange, Tullio Vardanega, and Francisco J. Cazorla. Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art. In 14th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 39, pp. 31-42, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2014)

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@InProceedings{fernandez_et_al:OASIcs.WCET.2014.31,
  author =	{Fernandez, Gabriel and Abella, Jaume and Qui\~{n}ones, Eduardo and Rochange, Christine and Vardanega, Tullio and Cazorla, Francisco J.},
  title =	{{Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art}},
  booktitle =	{14th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{31--42},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-69-9},
  ISSN =	{2190-6807},
  year =	{2014},
  volume =	{39},
  editor =	{Falk, Heiko},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2014.31},
  URN =		{urn:nbn:de:0030-drops-46027},
  doi =		{10.4230/OASIcs.WCET.2014.31},
  annote =	{Keywords: Contention, Multicores, WCET Analysis}
}
Document
DOI: 10.4230/OASIcs.WCET.2013.64
Upper-bounding Program Execution Time with Extreme Value Theory

Authors: Francisco J. Cazorla, Tullio Vardanega, Eduardo Quiñones, and Jaume Abella

Published in: OASIcs, Volume 30, 13th International Workshop on Worst-Case Execution Time Analysis (2013)

Abstract
In this paper we discuss the limitations of and the precautions to account for when using Extreme Value Theory (EVT) to compute upper bounds to the execution time of programs. We analyse the requirements placed by EVT on the observations to be made of the events of interest, and the conditions that render safe the computations of execution time upper bounds. We also study the requirements that a recent EVT-based timing analysis technique, Measurement-Based Probabilistic Timing Analysis (MBPTA), introduces, besides those imposed by EVT, on the computing system under analysis to increase the trustworthiness of the upper bounds that it computes.
Cite as

Francisco J. Cazorla, Tullio Vardanega, Eduardo Quiñones, and Jaume Abella. Upper-bounding Program Execution Time with Extreme Value Theory. In 13th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 30, pp. 64-76, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2013)

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@InProceedings{cazorla_et_al:OASIcs.WCET.2013.64,
  author =	{Cazorla, Francisco J. and Vardanega, Tullio and Qui\~{n}ones, Eduardo and Abella, Jaume},
  title =	{{Upper-bounding Program Execution Time with Extreme Value Theory}},
  booktitle =	{13th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{64--76},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-54-5},
  ISSN =	{2190-6807},
  year =	{2013},
  volume =	{30},
  editor =	{Maiza, Claire},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2013.64},
  URN =		{urn:nbn:de:0030-drops-41232},
  doi =		{10.4230/OASIcs.WCET.2013.64},
  annote =	{Keywords: WCET, Extreme Value Theory, Probabilistic, Deterministic}
}
Document
DOI: 10.4230/OASIcs.WCET.2013.97
Applying Measurement-Based Probabilistic Timing Analysis to Buffer Resources

Authors: Leonidas Kosmidis, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, and Francisco J. Cazorla

Published in: OASIcs, Volume 30, 13th International Workshop on Worst-Case Execution Time Analysis (2013)

Abstract
The use of complex hardware makes it difficult for current timing analysis techniques to compute trustworthy and tight worst-case execution time (WCET) bounds. Those techniques require detailed knowledge of the internal operation and state of the platform, at both the software and hardware level. Obtaining that information for modern hardware platforms is increasingly difficult. Measurement-Based Probabilistic Timing Analysis (MBPTA) reduces the cost of acquiring the knowledge needed for computing trustworthy and tight WCET bounds. MBPTA based on Extreme Value Theory requires the execution time of processor instructions to be independent and identically distributed (i.i.d.), which can be achieved with some hardware support. Previous proposals show how those properties can be achieved for caches. This paper considers, for the first time, the implications on MBPTA of using buffer resources. Buffers in general, and first-come first-served (FCFS) buffers in particular, are of paramount importance as the complexity of hardware increases, since they allow managing contention in those resources where multiple requests may be pending. We show how buffers can be used in the context of MBPTA and provide illustrative examples.
Cite as

Leonidas Kosmidis, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, and Francisco J. Cazorla. Applying Measurement-Based Probabilistic Timing Analysis to Buffer Resources. In 13th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 30, pp. 97-108, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2013)

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@InProceedings{kosmidis_et_al:OASIcs.WCET.2013.97,
  author =	{Kosmidis, Leonidas and Vardanega, Tullio and Abella, Jaume and Qui\~{n}ones, Eduardo and Cazorla, Francisco J.},
  title =	{{Applying Measurement-Based Probabilistic Timing Analysis to Buffer Resources}},
  booktitle =	{13th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{97--108},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-54-5},
  ISSN =	{2190-6807},
  year =	{2013},
  volume =	{30},
  editor =	{Maiza, Claire},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2013.97},
  URN =		{urn:nbn:de:0030-drops-41269},
  doi =		{10.4230/OASIcs.WCET.2013.97},
  annote =	{Keywords: WCET, Buffer, Probabilistic Timing Analysis}
}
Document
Complete Volume
DOI: 10.4230/OASIcs.WCET.2012
OASIcs, Volume 23, WCET'12, Complete Volume

Authors: Tullio Vardanega

Published in: OASIcs, Volume 23, 12th International Workshop on Worst-Case Execution Time Analysis (2012)

Abstract
OASIcs, Volume 23, WCET'12, Complete Volume
Cite as

12th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2012)

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@Proceedings{vardanega:OASIcs.WCET.2012,
  title =	{{OASIcs, Volume 23, WCET'12, Complete Volume}},
  booktitle =	{12th International Workshop on Worst-Case Execution Time Analysis},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-41-5},
  ISSN =	{2190-6807},
  year =	{2012},
  volume =	{23},
  editor =	{Vardanega, Tullio},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2012},
  URN =		{urn:nbn:de:0030-drops-35928},
  doi =		{10.4230/OASIcs.WCET.2012},
  annote =	{Keywords: \lbrackSpecial-Purpose and Application-Based Systems\rbrack: Real-time and embedded systems, \lbrackPerformance of systems\rbrack: Modelling techniques, Performance attribute Software/Program Verification, Testing and Debugging, \lbrackSoftware Engineering\rbrack: Software Architectures – Domain-specific architectures, Patterns}
}
Document
Front Matter
DOI: 10.4230/OASIcs.WCET.2012.i
Frontmatter, Table of Contents, Preface, Workshop Organization, List of Authors

Authors: Tullio Vardanega

Published in: OASIcs, Volume 23, 12th International Workshop on Worst-Case Execution Time Analysis (2012)

Abstract
Frontmatter, Table of Contents, Preface, Workshop Organization, List of Authors
Cite as

12th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 23, pp. i-xi, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2012)

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@InProceedings{vardanega:OASIcs.WCET.2012.i,
  author =	{Vardanega, Tullio},
  title =	{{Frontmatter, Table of Contents, Preface, Workshop Organization, List of Authors}},
  booktitle =	{12th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{i--xi},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-41-5},
  ISSN =	{2190-6807},
  year =	{2012},
  volume =	{23},
  editor =	{Vardanega, Tullio},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2012.i},
  URN =		{urn:nbn:de:0030-drops-35625},
  doi =		{10.4230/OASIcs.WCET.2012.i},
  annote =	{Keywords: Frontmatter, Table of Contents, Preface, Workshop Organization, List of Authors}
}
Document
DOI: 10.4230/OASIcs.WCET.2012.1
What is a Timing Anomaly?

Authors: Franck Cassez, René Rydhof Hansen, and Mads Chr. Olesen

Published in: OASIcs, Volume 23, 12th International Workshop on Worst-Case Execution Time Analysis (2012)

Abstract
Timing anomalies make worst-case execution time analysis much harder, because the analysis will have to consider all local choices. It has been widely recognised that certain hardware features are timing anomalous, while others are not. However, defining formally what a timing anomaly is, has been difficult. We examine previous definitions of timing anomalies, and identify examples where they do not align with common observations. We then provide a definition for consistently slower hardware traces that can be used to define timing anomalies and aligns with common observations.
Cite as

Franck Cassez, René Rydhof Hansen, and Mads Chr. Olesen. What is a Timing Anomaly?. In 12th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 23, pp. 1-12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2012)

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@InProceedings{cassez_et_al:OASIcs.WCET.2012.1,
  author =	{Cassez, Franck and Hansen, Ren\'{e} Rydhof and Olesen, Mads Chr.},
  title =	{{What is a Timing Anomaly?}},
  booktitle =	{12th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{1--12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-41-5},
  ISSN =	{2190-6807},
  year =	{2012},
  volume =	{23},
  editor =	{Vardanega, Tullio},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2012.1},
  URN =		{urn:nbn:de:0030-drops-35521},
  doi =		{10.4230/OASIcs.WCET.2012.1},
  annote =	{Keywords: Timing anomalies, worst case execution time (WCET), abstractions}
}
Document
DOI: 10.4230/OASIcs.WCET.2012.13
An Empirical Evaluation of the Influence of the Load-Store Unit on WCET Analysis

Authors: Mohamed Abdel Maksoud and Jan Reineke

Published in: OASIcs, Volume 23, 12th International Workshop on Worst-Case Execution Time Analysis (2012)

Abstract
Due to the complexity of today’s micro-architectures, the micro-architectural analysis usually constitutes the most time-consuming step in worst-case execution time (WCET) analysis. In this paper, we investigate the influence of the design of the load-store unit (LSU) in the PowerPC 7448 on WCET analysis. To this end, we introduce a simplified variant of the existing design of the LSU by reducing its queue sizes. Using AbsInt's aiT WCET analysis toolchain we determine the resulting WCET bounds and analysis times. For the modified version of the LSU with reduced queue sizes, analysis time is reduced by more than 50% on a set of benchmarks from the Mälardalen suite, while there is little change in the WCET bound.
Cite as

Mohamed Abdel Maksoud and Jan Reineke. An Empirical Evaluation of the Influence of the Load-Store Unit on WCET Analysis. In 12th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 23, pp. 13-24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2012)

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@InProceedings{abdelmaksoud_et_al:OASIcs.WCET.2012.13,
  author =	{Abdel Maksoud, Mohamed and Reineke, Jan},
  title =	{{An Empirical Evaluation of the Influence of the Load-Store Unit on WCET Analysis}},
  booktitle =	{12th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{13--24},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-41-5},
  ISSN =	{2190-6807},
  year =	{2012},
  volume =	{23},
  editor =	{Vardanega, Tullio},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2012.13},
  URN =		{urn:nbn:de:0030-drops-35536},
  doi =		{10.4230/OASIcs.WCET.2012.13},
  annote =	{Keywords: Empirical evaluation, architecture complexity effect, WCET analysis precision, WCET analysis performance, PowerPC 7448, Load-Store Unit}
}
Document
DOI: 10.4230/OASIcs.WCET.2012.25
Computing Same Block Relations for Relational Cache Analysis

Authors: Simon Wegener

Published in: OASIcs, Volume 23, 12th International Workshop on Worst-Case Execution Time Analysis (2012)

Abstract
In contrast to the classical cache analysis of Ferdinand, the relational cache analysis does not rely on precise address information. Instead, it uses same block relations between memory accesses to predict cache hits. The relational data cache analysis can thus also predict cache hits if fully unrolling a loop is not feasible during analysis, for example due to high memory consumption or long computation time. This paper proposes a static analysis based on abstract interpretation which is able to compute same block relations for relational cache analysis.
Cite as

Simon Wegener. Computing Same Block Relations for Relational Cache Analysis. In 12th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 23, pp. 25-37, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2012)

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@InProceedings{wegener:OASIcs.WCET.2012.25,
  author =	{Wegener, Simon},
  title =	{{Computing Same Block Relations for Relational Cache Analysis}},
  booktitle =	{12th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{25--37},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-41-5},
  ISSN =	{2190-6807},
  year =	{2012},
  volume =	{23},
  editor =	{Vardanega, Tullio},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2012.25},
  URN =		{urn:nbn:de:0030-drops-35544},
  doi =		{10.4230/OASIcs.WCET.2012.25},
  annote =	{Keywords: Cache Analysis, WCET Analysis, Real-time Systems, Static Program Analysis, Abstract Interpretation}
}
Document
DOI: 10.4230/OASIcs.WCET.2012.38
Toward Static Timing Analysis of Parallel Software

Authors: Andreas Gustavsson, Jan Gustafsson, and Björn Lisper

Published in: OASIcs, Volume 23, 12th International Workshop on Worst-Case Execution Time Analysis (2012)

Abstract
The current trend within computer, and even real-time, systems is to incorporate parallel hardware, e.g., multicore processors, and parallel software. Thus, the ability to safely analyse such parallel systems, e.g., regarding the timing behaviour, becomes necessary. Static timing analysis is an approach to mathematically derive safe bounds on the execution time of a program, when executed on a given hardware platform. This paper presents an algorithm that statically analyses the timing of parallel software, with threads communicating through shared memory, using abstract interpretation. It also gives an extensive example to clarify how the algorithm works.
Cite as

Andreas Gustavsson, Jan Gustafsson, and Björn Lisper. Toward Static Timing Analysis of Parallel Software. In 12th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 23, pp. 38-47, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2012)

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@InProceedings{gustavsson_et_al:OASIcs.WCET.2012.38,
  author =	{Gustavsson, Andreas and Gustafsson, Jan and Lisper, Bj\"{o}rn},
  title =	{{Toward Static Timing Analysis of Parallel Software}},
  booktitle =	{12th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{38--47},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-41-5},
  ISSN =	{2190-6807},
  year =	{2012},
  volume =	{23},
  editor =	{Vardanega, Tullio},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2012.38},
  URN =		{urn:nbn:de:0030-drops-35552},
  doi =		{10.4230/OASIcs.WCET.2012.38},
  annote =	{Keywords: Parallelism, BCET, WCET, Static analysis, Abstract interpretation}
}
Document
DOI: 10.4230/OASIcs.WCET.2012.48
Towards Parallel Programming Models for Predictability

Authors: Björn Lisper

Published in: OASIcs, Volume 23, 12th International Workshop on Worst-Case Execution Time Analysis (2012)

Abstract
Future embedded systems for performance-demanding applications will be massively parallel. High performance tasks will be parallel programs, running on several cores, rather than single threads running on single cores. For hard real-time applications, WCETs for such tasks must be bounded. Low-level parallel programming models, based on concurrent threads, are notoriously hard to use due to their inherent nondeterminism. Therefore the parallel processing community has long considered high-level parallel programming models, which restrict the low-level models to regain determinism. In this position paper we argue that such parallel programming models are beneficial also for WCET analysis of parallel programs. We review some proposed models, and discuss their influence on timing predictability. In particular we identify data parallel programming as a suitable paradigm as it is deterministic and allows current methods for WCET analysis to be extended to parallel code. GPUs are increasingly used for high performance applications: we discuss a current GPU architecture, and we argue that it offers a parallel platform for compute-intensive applications for which it seems possible to construct precise timing models. Thus, a promising route for the future is to develop WCET analyses for data-parallel software running on GPUs.
Cite as

Björn Lisper. Towards Parallel Programming Models for Predictability. In 12th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 23, pp. 48-58, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2012)

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@InProceedings{lisper:OASIcs.WCET.2012.48,
  author =	{Lisper, Bj\"{o}rn},
  title =	{{Towards Parallel Programming Models for Predictability}},
  booktitle =	{12th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{48--58},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-41-5},
  ISSN =	{2190-6807},
  year =	{2012},
  volume =	{23},
  editor =	{Vardanega, Tullio},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2012.48},
  URN =		{urn:nbn:de:0030-drops-35565},
  doi =		{10.4230/OASIcs.WCET.2012.48},
  annote =	{Keywords: Real-Time System, WCET analysis, Parallel Program, Data Parallelism}
}
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