Reducing Timing Interferences in Real-Time Applications Running on Multicore Architectures

Authors Thomas Carle, Hugues Cassé



PDF
Thumbnail PDF

File

OASIcs.WCET.2018.3.pdf
  • Filesize: 447 kB
  • 12 pages

Document Identifiers

Author Details

Thomas Carle
  • Université Paul Sabatier, IRIT, CNRS, Toulouse, France
Hugues Cassé
  • Université Paul Sabatier, IRIT, CNRS, Toulouse, France

Cite AsGet BibTex

Thomas Carle and Hugues Cassé. Reducing Timing Interferences in Real-Time Applications Running on Multicore Architectures. In 18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018). Open Access Series in Informatics (OASIcs), Volume 63, pp. 3:1-3:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)
https://doi.org/10.4230/OASIcs.WCET.2018.3

Abstract

We introduce a unified wcet analysis and scheduling framework for real-time applications deployed on multicore architectures. Our method does not follow a particular programming model, meaning that any piece of existing code (in particular legacy) can be re-used, and aims at reducing automatically the worst-case number of timing interferences between tasks. Our method is based on the notion of Time Interest Points (tips), which are instructions that can generate and/or suffer from timing interferences. We show how such points can be extracted from the binary code of applications and selected prior to performing the wcet analysis. We then represent real-time tasks as sequences of time intervals separated by tips, and schedule those tasks so that the overall makespan (including the potential timing penalties incurred by interferences) is minimized. This scheduling phase is performed using an Integer Linear Programming (ilp) solver. Preliminary results on state-of-the-art benchmarks show promising results and pave the way for future extensions of the model and optimizations.

Subject Classification

ACM Subject Classification
  • Software and its engineering → Automated static analysis
Keywords
  • Multicore architecture
  • WCET
  • Time Interest Points

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. A. Abel, F. Benz, J. Doerfert, B. Dörr, S. Hahn, F. Haupenthal, M. Jacobs, A. H. Moin, J. Reineke, B. Schommer, and R. Wilhelm. Impact of resource sharing on performance and performance prediction: A survey. In CONCUR, 2013. Google Scholar
  2. S. Altmeyer and C. Maiza Burguière. Cache-related preemption delay via useful cache blocks: Survey and redefinition. Journal of Systems Architecture, 2011. Google Scholar
  3. S. Altmeyer, R. I. Davis, L. Soares Indrusiak, C. Maiza, V. Nélis, and J. Reineke. A generic and compositional framework for multicore response time analysis. In RTNS, 2015. Google Scholar
  4. ARM. ARM Cortex-A Series - Programmer’s Guide for ARMv8 - A, v1.0 edition, 2015. Google Scholar
  5. C. Ballabriga, H. Cassé, C. Rochange, and P. Sainrat. Otawa: An open toolbox for adaptive wcet analysis. In Software Technologies for Embedded and Ubiquitous Systems, 2010. Google Scholar
  6. G. Durieu, M. Faugère, S. Girbal, D. Gracia Pérez, C. Pagetti, and W. Puffitsch. Predictable flight management system implementation on a multicore processor. In ERTS², 2014. Google Scholar
  7. C. Ferdinand and R. Wilhelm. On predicting data cache behavior for real-time systems. Lecture notes in computer science, 1998. Google Scholar
  8. J. Gustafsson, A. Betts, A. Ermedahl, and B. Lisper. The mälardalen WCET benchmarks: Past, present and future. In 10th International Workshop on Worst-Case Execution Time Analysis, WCET, 2010. Google Scholar
  9. IBM. Cplex user’s manual. https://www.ibm.com/support/knowledgecenter/SSSA5P_12.7.0/ilog.odms.studio.help/pdf/usrcplex.pdf, 2016.
  10. Infineon. AURIX TC27x D-Step (32-Bit Single-Chip Microcontroller) User’s Manual, v2.2, 2014. Google Scholar
  11. Y.-T. S. Li and S. Malik. Performance analysis of embedded software using implicit path enumeration. In Workshop on Languages, Compilers, and Tools for Real-Time Systems, 1995. Google Scholar
  12. C. Pagetti, J. Forget, F. Boniol, M. Cordovilla, and D. Lesens. Multi-task implementation of multi-periodic synchronous programs. Discrete Event Dynamic Systems, 21(3), 2011. URL: http://dx.doi.org/10.1007/s10626-011-0107-x.
  13. R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, and R. Kegley. A predictable execution model for cots-based embedded systems. RTAS, 2011. Google Scholar
  14. R. Pellizzoni, A. Schranzhofer, J.-J. Chen, M. Caccamo, and L. Thiele. Worst case delay analysis for memory interference in multicore systems. DATE, 2010. Google Scholar
  15. B. Rouxel, S. Derrien, and I. Puaut. Tightening contention delays while scheduling parallel applications on multi-core architectures. ACM Trans. Embed. Comput. Syst., 2017. Google Scholar
  16. A. Schranzhofer, J.-J. Chen, and L. Thiele. Timing analysis for tdma arbitration in resource sharing systems. RTAS, 2010. Google Scholar
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail