Document Open Access Logo

Pydrofoil: Accelerating Sail-Based Instruction Set Simulators

Authors Carl Friedrich Bolz-Tereick , Luke Panayi, Ferdia McKeogh , Tom Spink , Martin Berger

PDF

File

Thumbnail PDF
PDF
LIPIcs.ECOOP.2025.3.pdf
  • Filesize: 0.99 MB
  • 31 pages

Document Identifiers

Subject Classification

ACM Subject Classification
  • Software and its engineering → Retargetable compilers
  • Software and its engineering → Just-in-time compilers
  • Software and its engineering → Source code generation
  • Software and its engineering → Runtime environments
  • Software and its engineering → Domain specific languages
  • Hardware → Simulation and emulation
  • Software and its engineering → Interpreters
Keywords
  • Instruction set architecture
  • processor
  • domain-specific language
  • just-in-time compilation
  • meta-tracing

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads
    0
    Metadata Views

Abstract

We present Pydrofoil, a multi-stage compiler that generates instruction set simulators (ISSs) from processor instruction set architectures (ISAs) expressed in the high-level, verification-oriented ISA specification language Sail. Pydrofoil achieves a > 230× speedup over the C-based ISS generated by Sail on our benchmarks, thanks to the following insights. (i) An ISS is effectively an interpreter loop, and tracing just-in-time (JIT) compilers have proven effective at accelerating those, albeit mostly for dynamically typed languages. (ii) ISS workloads are highly atypical, dominated by intensive bit manipulation operations. Conventional compiler optimisations for general-purpose programming languages have limited impact for speeding up such workloads. We develop suitable domain-specific optimisations. (iii) Neither tracing JIT compilers, nor ahead-of-time (AOT) compilation alone, even with domain-specific optimisations, suffice for the generation of performant ISSs. Pydrofoil therefore implements a hybrid approach, pairing an AOT compiler with a tracing JIT built on the meta-tracing PyPy framework. AOT and JIT use domain-specific optimisations. Our benchmarks demonstrate that combining AOT and JIT compilers provides significantly greater performance gains than using either compiler alone.

Cite As Get BibTex

Carl Friedrich Bolz-Tereick, Luke Panayi, Ferdia McKeogh, Tom Spink, and Martin Berger. Pydrofoil: Accelerating Sail-Based Instruction Set Simulators. In 39th European Conference on Object-Oriented Programming (ECOOP 2025). Leibniz International Proceedings in Informatics (LIPIcs), Volume 333, pp. 3:1-3:31, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025) https://doi.org/10.4230/LIPIcs.ECOOP.2025.3

Author Details

Carl Friedrich Bolz-Tereick
  • Heinrich-Heine-Universität Düsseldorf, Germany
Luke Panayi
  • Imperial College London, UK
Ferdia McKeogh
  • University of St Andrews, UK
Tom Spink
  • University of St Andrews, UK
Martin Berger
  • University of Sussex, Brighton, UK
  • Montanarius Ltd, London, UK

Acknowledgements

We thank Alasdair Armstrong, Max Bernstein, Tobias Grosser, Tim Hutt, Alex Jeffery, Yutaka Nagashima, Amir Naseredini, Zdeněk Přikryl, Alastair Reid, Niyas Sait, Laurie Tratt, Mojtaba Valizadeh and the anonymous reviewers for their helpful comments. We thank Nico Rittinghaus for implementing Tristate numbers in the RPython JIT.

References

  1. Saar Amar, Tony Chen, David Chisnall, Felix Domke, Nathaniel Wesley Filardo, Kunyan Liu, Robert M. Norton, Yucong Tao, Murali Vijayaraghavan, Robert N. M. Watson, and Hongyan Xia. CHERIoT Architecture specification. CHERIoT Platform, version 0.6 (draft) edition, January 2025. URL: https://cheriot.org/cheriot-sail/cheriot-architecture.pdf.
  2. Saar Amar, David Chisnall, Tony Chen, Nathaniel Wesley Filardo, Ben Laurie, Kunyan Liu, Robert Norton, Simon W. Moore, Yucong Tao, Robert N. M. Watson, and Hongyan Xia. CHERIoT: Complete Memory Safety for Embedded Devices. In Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO '23, pages 641-653, New York, NY, USA, 2023. Association for Computing Machinery. URL: https://doi.org/10.1145/3613424.3614266.
  3. Davide Ancona, Massimo Ancona, Antonio Cuni, and Nicholas D. Matsakis. RPython: a step towards reconciling dynamically and statically typed OO languages. In Proceedings of the 2007 Symposium on Dynamic Languages, DLS '07, pages 53-64, New York, NY, USA, 2007. Association for Computing Machinery. URL: https://doi.org/10.1145/1297081.1297091.
  4. Arm. Arm Architecture FVPs. https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms/Arm%20Architecture%20FVPs. Accessed February 2025.
  5. Alasdair Armstrong, Thomas Bauereiss, Brian Campbell, and Shaked Flur. The Sail instruction-set semantics specification language. https://alasdair.github.io/. Accessed February 2025.
  6. Alasdair Armstrong, Thomas Bauereiss, Brian Campbell, Alastair Reid, Kathryn E. Gray, Robert M. Norton, Prashanth Mundkur, Mark Wassell, Jon French, Christopher Pulte, Shaked Flur, Ian Stark, Neel Krishnaswami, and Peter Sewell. ISA semantics for ARMv8-A, RISC-V, and CHERI-MIPS. In Proceedings of the 46th ACM SIGPLAN Symposium on Principles of Programming Languages, January 2019. Proc. ACM Program. Lang. 3, POPL, Article 71. URL: https://doi.org/10.1145/3290384.
  7. Alasdair Armstrong, Brian Campbell, Ben Simner, Thibaut Perami, and Peter Sewell. Isla. https://github.com/rems-project/isla, Accessed Jan. 2025.
  8. Krste Asanović and David A. Patterson. Instruction Sets Should Be Free: The Case For RISC-V. Technical Report UCB/EECS-2014-146, EECS Department, University of California, Berkeley, August 2014. URL: http://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.html.
  9. Vasanth Bala, Evelyn Duesterwald, and Sanjeev Banerjia. Dynamo: A Transparent Dynamic Optimization System. Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 46, February 2003. URL: https://doi.org/10.1145/349299.349303.
  10. Edd Barrett, Carl Friedrich Bolz-Tereick, Rebecca Killick, Sarah Mount, and Laurence Tratt. Virtual machine warmup blows hot and cold. Proceedings of the ACM on Programming Languages, 1(OOPSLA), October 2017. URL: https://doi.org/10.1145/3133876.
  11. Fabrice Bellard. QEMU, a fast and portable dynamic translator. In Proceedings of the Annual Conference on USENIX Annual Technical Conference, ATEC '05, page 41, USA, 2005. USENIX Association. Google Scholar
  12. Martin Berger and Laurence Tratt. Program Logics for Homogeneous Generative Run-Time Meta-Programming. Logical Methods in Computer Science (LMCS), 11(1:5), March 2015. URL: https://doi.org/10.2168/LMCS-11(1:5)2015.
  13. Carl Friedrich Bolz. Meta-Tracing Just-in-Time Compilation for RPython. PhD thesis, Heinrich-Heine-Universität Düsseldorf, 2014. Google Scholar
  14. Carl Friedrich Bolz, Antonio Cuni, Maciej Fijałkowski, Michael Leuschel, Samuele Pedroni, and Armin Rigo. Allocation removal by partial evaluation in a tracing JIT. In Proceedings of the 20th ACM SIGPLAN Workshop on Partial Evaluation and Program Manipulation, PEPM '11, pages 43-52, New York, NY, USA, 2011. Association for Computing Machinery. URL: https://doi.org/10.1145/1929501.1929508.
  15. Carl Friedrich Bolz, Antonio Cuni, Maciej Fijałkowski, and Armin Rigo. Tracing the meta-level: PyPy’s tracing JIT compiler. In Proceedings of the 4th Workshop on the Implementation, Compilation, Optimization of Object-Oriented Languages and Programming Systems, ICOOOLPS '09, pages 18-25, New York, NY, USA, 2009. Association for Computing Machinery. URL: https://doi.org/10.1145/1565824.1565827.
  16. Nils Bosbach, Niko Zurstraßen, Rebecca Pelke, Lukas Jünger, Jan Henrik Weinstock, and Rainer Leupers. Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models. In Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC '24, New York, NY, USA, 2024. Association for Computing Machinery. URL: https://doi.org/10.1145/3649329.3658257.
  17. James Bucek, Klaus-Dieter Lange, and Jóakim v. Kistowski. SPEC CPU2017: Next-Generation Compute Benchmark. In Companion of the 2018 ACM/SPEC International Conference on Performance Engineering, ICPE '18, pages 41-42, New York, NY, USA, 2018. Association for Computing Machinery. URL: https://doi.org/10.1145/3185768.3185771.
  18. Corrado Böhm and Giuseppe Jacopini. Flow Diagrams, Turing Machines And Languages With Only Two Formation Rules. Commun. ACM, 9(5):366-371, May 1966. URL: https://doi.org/10.1145/355592.365646.
  19. CHERIoT Platform. https://cheriot.org/. Accessed February 2025.
  20. C. Cifuentes and S. Sendall. Specifying the Semantics of Machine Instructions. In Proceedings of the 6th International Workshop on Program Comprehension, IWPC '98, page 126, USA, 1998. IEEE Computer Society. Google Scholar
  21. Codasip. What is CodAL? https://codasip.com/2021/02/26/what-is-codal/. Accessed February 2025.
  22. A. Fauth, J. Van Praet, and M. Freericks. Describing instruction set processors using nML. In Proceedings the European Design and Test Conference. ED&TC 1995, pages 503-507, 1995. URL: https://doi.org/10.1109/EDTC.1995.470354.
  23. Joseph Allen Fisher. The optimization of horizontal microcode within and beyond basic blocks: an application of processor scheduling with resources. PhD thesis, New York University, USA, 1979. AAI8010348. Google Scholar
  24. Joseph Allen Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Trans. Comput., 30(7):478-490, July 1981. URL: https://doi.org/10.1109/TC.1981.1675827.
  25. John Nathan Foster. Bidirectional Programming Languages. PhD thesis, University of Pennsylvania, 2009. URL: https://repository.upenn.edu/handle/20.500.14332/32277.
  26. MachineWare GmbH. Virtual Components Modeling Library (vcml). https://github.com/machineware-gmbh/vcml, Accessed February 2025.
  27. Michael Gordon, Robin Milner, Lockwood Morris, Malcom Newey, and Christopher Wadsworth. A Metalanguage for Interactive Proof in LCF. In Proceedings of the 5th ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages, pages 119-130. ACM, 1978. URL: https://doi.org/10.1145/512760.512773.
  28. George Hadjiyiannis, Silvina Hanono, and Srinivas Devadas. ISDL: an instruction set description language for retargetability. In Proceedings of the 34th Annual Design Automation Conference, DAC '97, pages 299-302, New York, NY, USA, 1997. Association for Computing Machinery. URL: https://doi.org/10.1145/266021.266108.
  29. A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau. EXPRESSION: a language for architecture exploration through compiler/simulator retargetability. In Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), pages 485-490, 1999. URL: https://doi.org/10.1109/DATE.1999.761170.
  30. David Harel. On folk theorems. Commun. ACM, 23(7):379-389, July 1980. URL: https://doi.org/10.1145/358886.358892.
  31. John Hauser. Berkeley SoftFloat. https://www.jhauser.us/arithmetic/SoftFloat.html. Accessed March 2025.
  32. IEEE Standard for Standard SystemC Language Reference Manual, 2023. URL: https://doi.org/10.1109/IEEESTD.2023.10246125.
  33. RISC-V International. ISA Formal Spec Public Review Public. https://github.com/riscvarchive/ISA_Formal_Spec_Public_Review. Accessed February 2025.
  34. RISC-V International. RISC-V Sail Model. https://github.com/riscv/sail-riscv. Accessed February 2025.
  35. Stephen Kyle, Igor Böhm, Björn Franke, Hugh Leather, and Nigel Topham. Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation. In Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems, LCTES '12, pages 21-30, New York, NY, USA, 2012. Association for Computing Machinery. URL: https://doi.org/10.1145/2248418.2248422.
  36. Nico Lehmann, Adam T. Geller, Niki Vazou, and Ranjit Jhala. Flux: Liquid Types for Rust. Proc. ACM Program. Lang., 7(PLDI), June 2023. URL: https://doi.org/10.1145/3591283.
  37. Jeffrey R. Lewis, John Launchbury, Erik Meijer, and Mark B. Shields. Implicit parameters: dynamic scoping with static types. In Proceedings of the 27th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL '00, pages 108-118, New York, NY, USA, 2000. Association for Computing Machinery. URL: https://doi.org/10.1145/325694.325708.
  38. Arm Limited. Fast Models: Develop Software without Hardware. https://www.arm.com/products/development-tools/simulation/fast-models. Accessed February 2025.
  39. Derek Lockhart, Berkin Ilbeyi, and Christopher Batten. Pydgin: generating fast instruction set simulators from simple architecture descriptions with meta-tracing JIT compilers. In 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 256-267, 2015. URL: https://doi.org/10.1109/ISPASS.2015.7095811.
  40. Robin Milner, Mads Tofte, Robert Harper, and David MacQueen. The Definition of Standard ML (Revised Edition). MIT Press, 1997. Google Scholar
  41. Prabhat Mishra and Nikil Dutt. Processor Description Languages. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2008. Google Scholar
  42. James George Mitchell. The design and construction of flexible and efficient interactive programming systems. PhD thesis, Carnegie Mellon University, USA, 1970. AAI7104538. Google Scholar
  43. Martin Odersky, Olivier Blanvillain, Fengyun Liu, Aggelos Biboudis, Heather Miller, and Sandro Stucki. Simplicitly: foundations and applications of implicit function types. Proc. ACM Program. Lang., 2(POPL), December 2017. URL: https://doi.org/10.1145/3158130.
  44. CHERIoT Platform. alloc.cc. https://github.com/CHERIoT-Platform/cheriot-rtos/blob/44c1bdeba1278354ec379e36d87fa33c6dc10b0c/benchmarks/allocation/alloc.cc. Accessed February 2025.
  45. CHERIoT Platform. CHERIoT RTOS. https://github.com/CHERIoT-Platform/cheriot-rtos/. Accessed February 2025.
  46. CHERIoT Platform. Cheriot specification and sail model. https://github.com/CHERIoT-Platform/cheriot-sail. Accessed February 2025.
  47. QEMU. System Emulation. https://www.qemu.org/docs/master/system/index.html. Accessed March 2025.
  48. QEMU.org. TCG Instruction Counting. https://www.qemu.org/docs/master/devel/tcg-icount.html. accessed February 2025.
  49. Norman Ramsey. Beyond Relooper: recursive translation of unstructured control flow to structured control flow (functional pearl). Proceedings of the ACM on Programming Languages, 6(ICFP):1-22, August 2022. URL: https://doi.org/10.1145/3547621.
  50. Allison Randal. The Ideal Versus the Real: Revisiting the History of Virtual Machines and Containers. ACM Comput. Surv., 53(1), February 2020. URL: https://doi.org/10.1145/3365199.
  51. Alastair Reid. Trustworthy specifications of ARM v8-A and v8-M system level architecture. In 2016 Formal Methods in Computer-Aided Design (FMCAD), pages 161-168, 2016. URL: https://doi.org/10.1109/FMCAD.2016.7886675.
  52. Cambridge University REMS Team. Github repo sail-arm. https://github.com/rems-project/sail-arm. Accessed February 2025.
  53. Armin Rigo and Samuele Pedroni. PyPy’s approach to virtual machine construction. In DLS, Portland, Oregon, USA, 2006. ACM. URL: https://doi.org/10.1145/1176617.1176753.
  54. S. Rigo, G. Araujo, M. Bartholomeu, and R. Azevedo. ArchC: a systemC-based architecture description language. In 16th Symposium on Computer Architecture and High Performance Computing, pages 66-73, 2004. URL: https://doi.org/10.1109/SBAC-PAD.2004.8.
  55. RISC-V model: riscv_insts_base. https://github.com/riscv/sail-riscv/blob/2dfc4ff9f2bed3dcd0a3e8748211c99099e70ab7/model/riscv_insts_base.sail#L159. Accessed February 2025.
  56. Patrick M. Rondon, Ming Kawaguci, and Ranjit Jhala. Liquid types. SIGPLAN Not., 43(6):159-169, June 2008. URL: https://doi.org/10.1145/1379022.1375602.
  57. Imperas Software. riscvOVPsim: A Complete, Fully Functional, Configurable RISC-V Simulator. https://github.com/riscv-ovpsim/imperas-riscv-tests/tree/v20230724/riscv-ovpsim. Accessed February 2025.
  58. Tom Spink, Harry Wagstaff, and Björn Franke. Efficient asynchronous interrupt handling in a full-system instruction set simulator. In Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, LCTES 2016, pages 1-10, New York, NY, USA, 2016. Association for Computing Machinery. URL: https://doi.org/10.1145/2907950.2907953.
  59. Tom Spink, Harry Wagstaff, and Björn Franke. Hardware-Accelerated Cross-Architecture Full-System Virtualization. ACM Trans. Archit. Code Optim., 13(4), October 2016. URL: https://doi.org/10.1145/2996798.
  60. Tom Spink, Harry Wagstaff, and Björn Franke. A Retargetable System-level DBT Hypervisor. ACM Trans. Comput. Syst., 36(4), May 2020. URL: https://doi.org/10.1145/3386161.
  61. Tom Spink, Harry Wagstaff, Björn Franke, and Nigel Topham. Efficient code generation in a region-based dynamic binary translator. In Proceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems, LCTES '14, pages 3-12, New York, NY, USA, 2014. Association for Computing Machinery. URL: https://doi.org/10.1145/2597809.2597810.
  62. Lukas Stadler, Thomas Würthinger, and Hanspeter Mössenböck. Partial Escape Analysis and Scalar Replacement for Java. In Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization, CGO '14, pages 165-174, New York, NY, USA, 2018. Association for Computing Machinery. URL: https://doi.org/10.1145/2544137.2544157.
  63. Standard performance evaluation corporation (SPEC) homepage. https://www.spec.org/spec/. Accessed February 2025.
  64. Gregory T. Sullivan, Derek L. Bruening, Iris Baron, Timothy Garnett, and Saman Amarasinghe. Dynamic native optimization of interpreters. In Proceedings of the 2003 Workshop on Interpreters, Virtual Machines and Emulators, IVME '03, pages 50-57, New York, NY, USA, 2003. Association for Computing Machinery. URL: https://doi.org/10.1145/858570.858576.
  65. Synopsys. ASIP Designer. https://www.synopsys.com/dw/ipdir.php?ds=asip-designer. Accessed February 2025.
  66. Synopsys. ImperasDV: RISC-V Processor Verification Made Easy. https://www.synopsys.com/verification/imperasdv.html. Accessed February 2025.
  67. Synopsys. Platform Architect: SoC architecture analysis and optimization for performance and power. https://www.synopsys.com/verification/virtual-prototyping/platform-architect.html. Accessed February 2025.
  68. Jubi Taneja, Zhengyang Liu, and John Regehr. Testing static analyses for precision and soundness. In Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization, CGO '20, pages 81-93, New York, NY, USA, 2020. Association for Computing Machinery. URL: https://doi.org/10.1145/3368826.3377927.
  69. GMP Development Team. GMP: The GNU Multiple Precision Arithmetic Library. https://gmplib.org/. Accessed February 2025.
  70. Niki Vazou. Liquid Haskell: Haskell as a Theorem Prover. PhD thesis, UC San Diego, 2016. URL: https://escholarship.org/uc/item/8dm057ws.
  71. Harishankar Vishwanathan, Matan Shachnai, Srinivas Narayana, and Santosh Nagarakatte. Sound, precise, and fast abstract interpretation with tristate numbers. In Proceedings of the 20th IEEE/ACM International Symposium on Code Generation and Optimization, CGO '22, pages 254-265. IEEE Press, 2022. URL: https://doi.org/10.1109/CGO53902.2022.9741267.
  72. Harry Wagstaff. From High Level Architecture Descriptions to Fast Instruction Set Simulators. PhD thesis, School of Informatics, University of Edinburgh, 2015. Google Scholar
  73. Harry Wagstaff, Miles Gould, Björn Franke, and Nigel Topham. Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description. In 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pages 1-6, 2013. URL: https://doi.org/10.1145/2463209.2488760.
  74. Harry Wagstaff, Tom Spink, and Björn Franke. Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulators. In Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES '14, New York, NY, USA, 2014. Association for Computing Machinery. URL: https://doi.org/10.1145/2656106.2656113.
  75. Andrew Waterman. Design of the RISC-V Instruction Set Architecture. PhD thesis, EECS Department, University of California, Berkeley, January 2016. URL: http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.html.
  76. Andrew Waterman and Krste Asanović, editors. The RISC-V Instruction Set Manual, Volume I: User-Level ISA. RISC-V International, December 2019. Document Version 20191214-draft. Google Scholar
  77. Andrew Waterman and Krste Asanović, editors. The RISC-V Instruction Set Manual, Volume II: Privileged Architecture. RISC-V International, December 2021. Document Version 20211203. Google Scholar
  78. Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, Graeme Barnes, David Chisnall, Jessica Clarke, Brooks Davis, Lee Eisen, Nathaniel Wesley Filardo, Franz A. Fuchs, Richard Grisenthwaite, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alexander Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia. Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 9). Technical Report UCAM-CL-TR-987, University of Cambridge, Computer Laboratory, September 2023. URL: https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-987.pdf.
  79. Wikipedia contributors. Initial ramdisk - Wikipedia, the free encyclopedia, 2025. [Online; accessed 2-March-2025]. URL: https://en.wikipedia.org/w/index.php?title=Initial_ramdisk&oldid=1277729657.
  80. Hongwei Xi. Dependent ML: An approach to practical programming with dependent types. J. Funct. Program., 17(2):215-286, March 2007. URL: https://doi.org/10.1017/S0956796806006216.
  81. Alon Zakai. Emscripten: an LLVM-to-JavaScript compiler. In Proceedings of the ACM international conference companion on Object oriented programming systems languages and applications companion, OOPSLA '11, pages 301-312, New York, NY, USA, October 2011. Association for Computing Machinery. URL: https://doi.org/10.1145/2048147.2048224.
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail
© 2023-2025 Schloss Dagstuhl – LZI GmbH About DROPS Imprint Privacy Contact