@InProceedings{schlickling_et_al:OASIcs.WCET.2007.1189,
  author =	{Schlickling, Marc and Pister, Markus},
  title =	{{A Framework for Static Analysis of VHDL Code}},
  booktitle =	{7th International Workshop on Worst-Case Execution Time Analysis (WCET'07)},
  pages =	{1--6},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-05-7},
  ISSN =	{2190-6807},
  year =	{2007},
  volume =	{6},
  editor =	{Rochange, Christine},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2007.1189},
  URN =		{urn:nbn:de:0030-drops-11891},
  doi =		{10.4230/OASIcs.WCET.2007.1189},
  annote =	{Keywords: Timing Analysis, Worst-Case Execution Time, VHDL, Static Analysis}
}