@InProceedings{lofwenmark_et_al:OASIcs.WCET.2016.12,
  author =	{L\"{o}fwenmark, Andreas and Nadjm-Tehrani, Simin},
  title =	{{Understanding Shared Memory Bank Access Interference in Multi-Core Avionics}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{12:1--12:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.12},
  URN =		{urn:nbn:de:0030-drops-69051},
  doi =		{10.4230/OASIcs.WCET.2016.12},
  annote =	{Keywords: multi-core, avionics, shared memory systems, WCET}
}