@Article{papadopoulos_et_al:DARTS.6.1.0,
  author =	{Papadopoulos, Alessandro V. and Biondi, Alessandro},
  title =	{{Front Matter, Table of Contents, Preface, Conference Organization}},
  pages =	{0:i--0:x},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Papadopoulos, Alessandro V. and Biondi, Alessandro},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.6.1.0},
  URN =		{urn:nbn:de:0030-drops-123904},
  doi =		{10.4230/DARTS.6.1.0},
  annote =	{Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
@Article{osborne_et_al:DARTS.6.1.1,
  author =	{Osborne, Sims Hill and Bakita, Joshua J. and Anderson, James H.},
  title =	{{Simultaneous Multithreading and Hard Real Time: Can it be Safe? (Artifact)}},
  pages =	{1:1--1:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Osborne, Sims Hill and Bakita, Joshua J. and Anderson, James H.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.6.1.1},
  URN =		{urn:nbn:de:0030-drops-123915},
  doi =		{10.4230/DARTS.6.1.1},
  annote =	{Keywords: real-time systems, simultaneous multithreading, real-time, scheduling algorithms, timing analysis, probability, statistics}
}
@Article{deoliveira_et_al:DARTS.6.1.2,
  author =	{de Oliveira, Daniel Bristot and Casini, Daniel and de Oliveira, R\^{o}mulo Silva and Cucinotta, Tommaso},
  title =	{{Demystifying the Real-Time Linux Scheduling Latency (Artifact)}},
  pages =	{2:1--2:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{de Oliveira, Daniel Bristot and Casini, Daniel and de Oliveira, R\^{o}mulo Silva and Cucinotta, Tommaso},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.6.1.2},
  URN =		{urn:nbn:de:0030-drops-123928},
  doi =		{10.4230/DARTS.6.1.2},
  annote =	{Keywords: Real-time operating systems, Linux kernel, PREEMPT\underlineRT, Scheduling latency}
}
@Article{bozhko_et_al:DARTS.6.1.3,
  author =	{Bozhko, Sergey and Brandenburg, Bj\"{o}rn B.},
  title =	{{Abstract Response-Time Analysis: A Formal Foundation for the Busy-Window Principle (Artifact)}},
  pages =	{3:1--3:2},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Bozhko, Sergey and Brandenburg, Bj\"{o}rn B.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.6.1.3},
  URN =		{urn:nbn:de:0030-drops-123930},
  doi =		{10.4230/DARTS.6.1.3},
  annote =	{Keywords: hard real-time systems, response-time analysis, uniprocessor, busy window, fixed priority, EDF, verification, Coq, Prosa, preemptive, non-preemptive, limited-preemptive}
}
@Article{restuccia_et_al:DARTS.6.1.4,
  author =	{Restuccia, Francesco and Pagani, Marco and Biondi, Alessandro and Marinoni, Mauro and Buttazzo, Giorgio},
  title =	{{Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact)}},
  pages =	{4:1--4:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Restuccia, Francesco and Pagani, Marco and Biondi, Alessandro and Marinoni, Mauro and Buttazzo, Giorgio},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.6.1.4},
  URN =		{urn:nbn:de:0030-drops-123941},
  doi =		{10.4230/DARTS.6.1.4},
  annote =	{Keywords: Heterogeneous computing, Predictable hardware acceleration, FPGA SoCs, Multi-Master architectures}
}
@Article{jacob_et_al:DARTS.6.1.5,
  author =	{Jacob, Romain and Zhang, Licong and Zimmerling, Marco and Beutel, Jan and Chakraborty, Samarjit and Thiele, Lothar},
  title =	{{The Time-Triggered Wireless Architecture (Artifact)}},
  pages =	{5:1--5:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Jacob, Romain and Zhang, Licong and Zimmerling, Marco and Beutel, Jan and Chakraborty, Samarjit and Thiele, Lothar},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.6.1.5},
  URN =		{urn:nbn:de:0030-drops-123952},
  doi =		{10.4230/DARTS.6.1.5},
  annote =	{Keywords: Time-triggered architecture, wireless bus, synchronous transmissions}
}