Dagstuhl Seminar Proceedings, Volume 6141,

• Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas 06141 Abstracts Collection – Dynamically Reconfigurable Architectures 10.4230/DagSemProc.06141.1
• Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas 06141 Executive Summary – Dynamically Reconfigurable Architectures 10.4230/DagSemProc.06141.2
• Norbert Wehn, Timo Vogt, and Christian Neeb A Reconfigurable Outer Modem Platform for Future Communications Systems 10.4230/DagSemProc.06141.3
• József Vásárhelyi and Péter Serfözö Analysis of Mojette Transform Implementation on Reconfigurable Hardware 10.4230/DagSemProc.06141.4
• Diana Göhringer, Mateusz Majer, and Jürgen Teich Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine 10.4230/DagSemProc.06141.5
• Walter Stechele Dynamically Reconfigurable Systems-on-Chip 10.4230/DagSemProc.06141.6
• Gerard J.M. Smit, Andre B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, and Paul M. Heysters Efficient architectures for streaming applications 10.4230/DagSemProc.06141.7
• Oliver Diessel and Shannon Koh Enabling RTR for industry 10.4230/DagSemProc.06141.8
• Sven Heithecker, Amilcar do Carmo Lucas, and Rolf Ernst FlexFilm - an Image Processor for Digital Film Processing 10.4230/DagSemProc.06141.9
• David Kearney and Mark Jasiunas Managing power amongst a group of networked embedded fpgas using dynamic reconfiguration and task migration 10.4230/DagSemProc.06141.10
• Jürgen Becker, Michael Hübner, and Katarina Paulsson Physical 2D Morphware and Power Reduction Methods for Everyone 10.4230/DagSemProc.06141.11
• Douglas Maskell and Timothy F. Oliver Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System 10.4230/DagSemProc.06141.12
• Sunil Shukla, Neil W. Bergmann, and Jürgen Becker QUKU: A Coarse Grained Paradigm for FPGAs 10.4230/DagSemProc.06141.13
• Rainer Buchty Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution 10.4230/DagSemProc.06141.14
• Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, and Thomas Wild Reconfigurable Processing Units vs. Reconfigurable Interconnects 10.4230/DagSemProc.06141.15
• Florian Dittmann Reconfiguration Time Aware Processing on FPGAs 10.4230/DagSemProc.06141.16
• Klaus Waldschmidt, Jan Haase, Andreas Hofmann, Markus Damm, and Dennis Hauser Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs) 10.4230/DagSemProc.06141.17
• Peter M. Athanas The (empty?) Promise of FPGA Supercomputing 10.4230/DagSemProc.06141.18
• Peter Zipf and Manfred Glesner Towards an Automated Design of Application-specific Reconfigurable Logic 10.4230/DagSemProc.06141.19