@Proceedings{schoeberl:OASIcs.WCET.2016,
  title =	{{OASIcs, Volume 55, WCET'16, Complete Volume}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016},
  URN =		{urn:nbn:de:0030-drops-69095},
  doi =		{10.4230/OASIcs.WCET.2016},
  annote =	{Keywords: Performance Analysis and Design Aids, Real-Time and Embedded systems, Software/- Program Verification, \lbrackOrganization and Design\rbrack Real-time Systems and Embedded Systems}
}
@InProceedings{schoeberl:OASIcs.WCET.2016.0,
  author =	{Schoeberl, Martin},
  title =	{{Front Matter, Table of Contents, Preface, List of Authors, Committee}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{0:i--0:xii},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.0},
  URN =		{urn:nbn:de:0030-drops-68939},
  doi =		{10.4230/OASIcs.WCET.2016.0},
  annote =	{Keywords: Front Matter, Table of Contents, Preface, List of Authors, Committee}
}
@InProceedings{diaz_et_al:OASIcs.WCET.2016.1,
  author =	{D{\'\i}az, Enrique and Abella, Jaume and Mezzetti, Enrico and Agirre, Irune and Azkarate-Askasua, Mikel and Vardanega, Tullio and Cazorla, Francisco J.},
  title =	{{Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{1:1--1:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.1},
  URN =		{urn:nbn:de:0030-drops-68946},
  doi =		{10.4230/OASIcs.WCET.2016.1},
  annote =	{Keywords: WCET, Measurements, Instrumentation overhead}
}
@InProceedings{falk_et_al:OASIcs.WCET.2016.2,
  author =	{Falk, Heiko and Altmeyer, Sebastian and Hellinckx, Peter and Lisper, Bj\"{o}rn and Puffitsch, Wolfgang and Rochange, Christine and Schoeberl, Martin and S{\o}rensen, Rasmus Bo and W\"{a}gemann, Peter and Wegener, Simon},
  title =	{{TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{2:1--2:10},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.2},
  URN =		{urn:nbn:de:0030-drops-68958},
  doi =		{10.4230/OASIcs.WCET.2016.2},
  annote =	{Keywords: Benchmark, WCET analysis, real-time systems}
}
@InProceedings{mussot_et_al:OASIcs.WCET.2016.3,
  author =	{Mussot, Vincent and Ruiz, Jordy and Sotin, Pascal and de Michiel, Marianne and Cass\'{e}, Hugues},
  title =	{{Expressing and Exploiting Conflicts over Paths in WCET Analysis}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{3:1--3:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.3},
  URN =		{urn:nbn:de:0030-drops-68966},
  doi =		{10.4230/OASIcs.WCET.2016.3},
  annote =	{Keywords: WCET analysis, Infeasible paths, Path conflicts, IPET, CFG transformation}
}
@InProceedings{dreyer_et_al:OASIcs.WCET.2016.4,
  author =	{Dreyer, Boris and Hochberger, Christian and Lange, Alexander and Wegener, Simon and Weiss, Alexander},
  title =	{{Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{4:1--4:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.4},
  URN =		{urn:nbn:de:0030-drops-68977},
  doi =		{10.4230/OASIcs.WCET.2016.4},
  annote =	{Keywords: Hybrid Worst-Case Execution Time (WCET) Estimation for Multicore Processors, Real-time Systems}
}
@InProceedings{naji_et_al:OASIcs.WCET.2016.5,
  author =	{Naji, Amine and Brandner, Florian},
  title =	{{Eager Stack Cache Memory Transfers}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{5:1--5:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.5},
  URN =		{urn:nbn:de:0030-drops-68983},
  doi =		{10.4230/OASIcs.WCET.2016.5},
  annote =	{Keywords: Predictability, Eager Memory Transfers, Stack Cache, Real-Time Systems, Prefetching, Eager Eviction}
}
@InProceedings{nelis_et_al:OASIcs.WCET.2016.6,
  author =	{N\'{e}lis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel},
  title =	{{The Variability of Application Execution Times on a Multi-Core Platform}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{6:1--6:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.6},
  URN =		{urn:nbn:de:0030-drops-68994},
  doi =		{10.4230/OASIcs.WCET.2016.6},
  annote =	{Keywords: Execution time variability, timing analysis, WCET estimates, multi-cores, many-cores}
}
@InProceedings{mangean_et_al:OASIcs.WCET.2016.7,
  author =	{Mangean, Armel and B\'{e}chennec, Jean-Luc and Briday, Mika\"{e}l and Faucou, S\'{e}bastien},
  title =	{{BEST: a Binary Executable Slicing Tool}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{7:1--7:10},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.7},
  URN =		{urn:nbn:de:0030-drops-69004},
  doi =		{10.4230/OASIcs.WCET.2016.7},
  annote =	{Keywords: Program Slicing, Binary Code Analysis, WCET Analysis}
}
@InProceedings{sun_et_al:OASIcs.WCET.2016.8,
  author =	{Sun, Wei-Tsun and Cass\'{e}, Hugues},
  title =	{{Dynamic Branch Resolution Based on Combined Static Analyses}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{8:1--8:10},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.8},
  URN =		{urn:nbn:de:0030-drops-69014},
  doi =		{10.4230/OASIcs.WCET.2016.8},
  annote =	{Keywords: WCET, static analysis, dynamic branch, assembly, machine language}
}
@InProceedings{kosmidis_et_al:OASIcs.WCET.2016.9,
  author =	{Kosmidis, Leonidas and Compagnin, Davide and Morales, David and Mezzetti, Enrico and Quinones, Eduardo and Abella, Jaume and Vardanega, Tullio and Cazorla, Francisco J.},
  title =	{{Measurement-Based Timing Analysis of the AURIX Caches}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{9:1--9:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.9},
  URN =		{urn:nbn:de:0030-drops-69028},
  doi =		{10.4230/OASIcs.WCET.2016.9},
  annote =	{Keywords: WCET, caches, AURIX, Automotive}
}
@InProceedings{frieb_et_al:OASIcs.WCET.2016.10,
  author =	{Frieb, Martin and Stegmeier, Alexander and Mische, J\"{o}rg and Ungerer, Theo},
  title =	{{Employing MPI Collectives for Timing Analysis on Embedded Multi-Cores}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{10:1--10:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.10},
  URN =		{urn:nbn:de:0030-drops-69034},
  doi =		{10.4230/OASIcs.WCET.2016.10},
  annote =	{Keywords: Real Time, Network on Chip, WCET, Timing Analysis, MPI}
}
@InProceedings{rochange:OASIcs.WCET.2016.11,
  author =	{Rochange, Christine},
  title =	{{Parallel Real-Time Tasks, as Viewed by WCET Analysis and Task Scheduling Approaches}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{11:1--11:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.11},
  URN =		{urn:nbn:de:0030-drops-69048},
  doi =		{10.4230/OASIcs.WCET.2016.11},
  annote =	{Keywords: multicore, parallel tasks, worst-case execution time analysis, schedulability, worst-case response time analysis}
}
@InProceedings{lofwenmark_et_al:OASIcs.WCET.2016.12,
  author =	{L\"{o}fwenmark, Andreas and Nadjm-Tehrani, Simin},
  title =	{{Understanding Shared Memory Bank Access Interference in Multi-Core Avionics}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{12:1--12:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.12},
  URN =		{urn:nbn:de:0030-drops-69051},
  doi =		{10.4230/OASIcs.WCET.2016.12},
  annote =	{Keywords: multi-core, avionics, shared memory systems, WCET}
}