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          <dc:title>Optimal Register Construction in M&amp;M Systems</dc:title>
          <dc:creator>Hadzilacos, Vassos</dc:creator>
          <dc:creator>Hu, Xing</dc:creator>
          <dc:creator>Toueg, Sam</dc:creator>
          <dc:subject>asynchronous distributed system</dc:subject>
          <dc:subject>shared memory</dc:subject>
          <dc:subject>message passing</dc:subject>
          <dc:description>Motivated by recent distributed systems technology, Aguilera et al. introduced a hybrid model of distributed computing, called message-and-memory model or m&amp;m model for short [Marcos K. Aguilera et al., 2018]. In this model, processes can communicate by message passing and also by accessing some shared memory. We consider the basic problem of implementing an atomic single-writer multi-reader (SWMR) register shared by all the processes in m&amp;m systems. Specifically, we give an algorithm that implements such a register in m&amp;m systems and show that it is optimal in the number of process crashes that it can tolerate. This generalizes the well-known implementation of an atomic SWMR register in a pure message-passing system [Attiya et al., 1995].</dc:description>
          <dc:publisher>Schloss Dagstuhl – Leibniz-Zentrum für Informatik</dc:publisher>
          <dc:contributor>Vassos Hadzilacos and Xing Hu and Sam Toueg</dc:contributor>
          <dc:date>2020</dc:date>
          <dc:relation>Is Part Of LIPIcs, Volume 153, 23rd International Conference on Principles of Distributed Systems (OPODIS 2019)</dc:relation>
          <dc:type>InProceedings</dc:type>
          <dc:type>Text</dc:type>
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          <dc:identifier>doi:10.4230/LIPIcs.OPODIS.2019.28</dc:identifier>
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          <dc:language>eng</dc:language>
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