2026-08-17T12:31:46Z https://drops.dagstuhl.de/oai

oai:drops-oai.dagstuhl.de:12394 2024-03-06T11:05:08Z ddc:004 open_access

Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact) Restuccia, Francesco Pagani, Marco Biondi, Alessandro Marinoni, Mauro Buttazzo, Giorgio Heterogeneous computing Predictable hardware acceleration FPGA SoCs Multi-Master architectures This artifact provides the means for reproducing the experiments presented in the paper "Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoC". In particular, it provides the means and describes how to replicate the experimental study that has been carried out to evaluate the proposed analysis with synthetic workloads. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Francesco Restuccia and Marco Pagani and Alessandro Biondi and Mauro Marinoni and Giorgio Buttazzo 2020 Is Part Of DARTS, Volume 6, Issue 1, Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020) Article Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/DARTS.6.1.4 urn:nbn:de:0030-drops-123941 https://drops.dagstuhl.de/entities/document/10.4230/DARTS.6.1.4 eng https://creativecommons.org/licenses/by/3.0/legalcode