<?xml version="1.0" encoding="UTF-8"?>
<OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd">
  <responseDate>2026-07-25T11:56:02Z</responseDate>
  <request identifier="13933" metadataPrefix="oai_dc" verb="GetRecord">https://drops.dagstuhl.de/oai</request>
  <GetRecord>
    <record>
      <header>
        <identifier>oai:drops-oai.dagstuhl.de:13933</identifier>
        <datestamp>2024-03-12T11:59:55Z</datestamp>
        <setSpec>ddc:004</setSpec>
        <setSpec>open_access</setSpec>
      </header>
      <metadata>
        <oai_dc:dc xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd">
          <dc:title>A Memory Scheduling Infrastructure for Multi-Core Systems with Re-Programmable Logic</dc:title>
          <dc:creator>Hoornaert, Denis</dc:creator>
          <dc:creator>Roozkhosh, Shahin</dc:creator>
          <dc:creator>Mancuso, Renato</dc:creator>
          <dc:subject>Memory Scheduling</dc:subject>
          <dc:subject>PLIM</dc:subject>
          <dc:subject>FPGA</dc:subject>
          <dc:subject>Memory Management</dc:subject>
          <dc:subject>Bandwidth Regulation</dc:subject>
          <dc:subject>MemGuard</dc:subject>
          <dc:subject>Coloring</dc:subject>
          <dc:subject>Bank Partitioning</dc:subject>
          <dc:subject>Real-time</dc:subject>
          <dc:subject>Multicore</dc:subject>
          <dc:subject>Safety-critical</dc:subject>
          <dc:description>The sharp increase in demand for performance has prompted an explosion in the complexity of modern multi-core embedded systems. This has lead to unprecedented temporal unpredictability concerns in Cyber-Physical Systems (CPS). On-chip integration of programmable logic (PL) alongside a conventional Processing System (PS) in modern Systems-on-Chip (SoC) establishes a genuine compromise between specialization, performance, and reconfigurability. In addition to typical use-cases, it has been shown that the PL can be used to observe, manipulate, and ultimately manage memory traffic generated by a traditional multi-core processor.&#13;
This paper explores the possibility of PL-aided memory scheduling by proposing a Scheduler In-the-Middle (SchIM). We demonstrate that the SchIM enables transaction-level control over the main memory traffic generated by a set of embedded cores. Focusing on extensibility and reconfigurability, we put forward a SchIM design covering two main objectives. First, to provide a safe playground to test innovative memory scheduling mechanisms; and second, to establish a transition path from software-based memory regulation to provably correct hardware-enforced memory scheduling. We evaluate our design through a full-system implementation on a commercial PS-PL platform using synthetic and real-world benchmarks.</dc:description>
          <dc:publisher>Schloss Dagstuhl – Leibniz-Zentrum für Informatik</dc:publisher>
          <dc:contributor>Denis Hoornaert and Shahin Roozkhosh and Renato Mancuso</dc:contributor>
          <dc:date>2021</dc:date>
          <dc:relation>Is Part Of LIPIcs, Volume 196, 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)</dc:relation>
          <dc:type>InProceedings</dc:type>
          <dc:type>Text</dc:type>
          <dc:type>doc-type:ResearchArticle</dc:type>
          <dc:type>publishedVersion</dc:type>
          <dc:format>application/pdf</dc:format>
          <dc:identifier>doi:10.4230/LIPIcs.ECRTS.2021.2</dc:identifier>
          <dc:identifier>urn:nbn:de:0030-drops-139331</dc:identifier>
          <dc:identifier>https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2021.2</dc:identifier>
          <dc:language>eng</dc:language>
          <dc:rights>https://creativecommons.org/licenses/by/4.0/legalcode</dc:rights>
        </oai_dc:dc>
      </metadata>
    </record>
  </GetRecord>
</OAI-PMH>
