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        <identifier>oai:drops-oai.dagstuhl.de:16333</identifier>
        <datestamp>2024-03-06T10:57:40Z</datestamp>
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          <dc:title>Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds</dc:title>
          <dc:creator>Mirosanlou, Reza</dc:creator>
          <dc:creator>Hassan, Mohamed</dc:creator>
          <dc:creator>Pellizzoni, Rodolfo</dc:creator>
          <dc:subject>Predictability</dc:subject>
          <dc:subject>Cache</dc:subject>
          <dc:subject>COTS</dc:subject>
          <dc:subject>Arbitration</dc:subject>
          <dc:subject>Real-time system</dc:subject>
          <dc:description>In Commercial-Off-The-Shelf (COTS) systems-on-chip, processing elements communicate data through a shared memory hierarchy, and a coherent high-performance interconnect, where the de facto standard to handle shared data is through a coherence protocol. Driven by the extraordinary demands from modern real-time embedded system applications to generate, process, and communicate massive amounts of data, recent efforts aim to ensure timing predictability while integrating cache coherence in multi-core real-time systems. However, we observe that most of these efforts compromise system average performance upon offering predictability guarantees. Motivated by this observation, this work proposes an arbiter aimed at providing a predictable, coherent shared cache hierarchy solution, yet with a negligible performance degradation compared to COTS solutions. We achieve this goal by adopting a high-performance-driven architecture including a split-transaction bus and bankized shared cache. In addition, all accesses are arbitrated through a global ordering mechanism. Our proposed arbiter operates alongside conventional coherence protocols without requiring any protocol modifications. Furthermore, we leverage the Duetto reference model by pairing the proposed arbiter and a high-performance arbiter. We evaluate our solution based on both synthetic and SPLASH-3 benchmarks, showing that we can significantly outperform the state-of-the-art in predictable cache coherence, while offering a COTS-level performance.</dc:description>
          <dc:publisher>Schloss Dagstuhl – Leibniz-Zentrum für Informatik</dc:publisher>
          <dc:contributor>Reza Mirosanlou and Mohamed Hassan and Rodolfo Pellizzoni</dc:contributor>
          <dc:date>2022</dc:date>
          <dc:relation>Is Part Of LIPIcs, Volume 231, 34th Euromicro Conference on Real-Time Systems (ECRTS 2022)</dc:relation>
          <dc:type>InProceedings</dc:type>
          <dc:type>Text</dc:type>
          <dc:type>doc-type:ResearchArticle</dc:type>
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          <dc:identifier>doi:10.4230/LIPIcs.ECRTS.2022.16</dc:identifier>
          <dc:identifier>urn:nbn:de:0030-drops-163330</dc:identifier>
          <dc:identifier>https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2022.16</dc:identifier>
          <dc:language>eng</dc:language>
          <dc:rights>https://creativecommons.org/licenses/by/4.0/legalcode</dc:rights>
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