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Traces as a Solution to Pessimism and Modeling Costs in WCET Analysis Whitham, Jack Audsley, Neil WCET superscalar cpu virtual traces WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior. CPU hardware modifications could be used to constrain operations to known execution paths called traces, permitting exploitation of instruction level parallelism with guaranteed timing. Previous implementations of traces have used microcode to constrain operations, but other possibilities exist. A new implementation strategy (virtual traces) is introduced here. In this paper the benefits and costs of traces are discussed. Advantages of traces include a reduction in pessimism in WCET analysis, with the need to accurately model CPU internals removed. Disadvantages of traces include a reduction of peak throughput of the CPU, a need for deterministic memory and a potential increase in the complexity of WCET models. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Jack Whitham and Neil Audsley 2008 Is Part Of OASIcs, Volume 8, 8th International Workshop on Worst-Case Execution Time Analysis (WCET'08) (2008) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/OASIcs.WCET.2008.1666 urn:nbn:de:0030-drops-16666 https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2008.1666 eng https://creativecommons.org/licenses/by-nc-nd/3.0/legalcode