2026-07-23T08:46:47Z https://drops.dagstuhl.de/oai

oai:drops-oai.dagstuhl.de:17726 2024-03-12T12:01:12Z ddc:004 open_access

Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments Piccoli, Michele Zoni, Davide Fornaciari, William Massari, Giuseppe Cococcioni, Marco Rossi, Federico Saponara, Sergio Ruffaldi, Emanuele power estimation computer arithmetic posit numbers Since its introduction in 2017, the Posit™ format for representing real numbers has attracted a lot of interest, as an alternative to IEEE 754 floating point representation. Several hardware implementations of arithmetic operations between posit numbers have also been proposed in recent years. In this work, we analyze the dynamic power consumption of the Full Posit Processing Unit (FPPU) recently developed at the University of Pisa. Experimental results show that we can model the dynamic power consumption of the FPPU with an acceptable approximation error from 2.84% (32-bit FPPU) to 7.32% (8-bit FPPU). Furthermore, from the synthesis of the power monitoring unit alongside the FPPU we demonstrate that the additional power module has an area cost that goes from ∼5% (32-bit FPPU) to ∼30% (8-bit FPPU) of the total unit area occupation. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Michele Piccoli and Davide Zoni and William Fornaciari and Giuseppe Massari and Marco Cococcioni and Federico Rossi and Sergio Saponara and Emanuele Ruffaldi 2023 Is Part Of OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/OASIcs.PARMA-DITAM.2023.6 urn:nbn:de:0030-drops-177268 https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.6 eng https://creativecommons.org/licenses/by/4.0/legalcode