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Methods and Metrics for Reliability Assessment Alves de Barros-Naviner, Lirida Naviner, Jean-François Teixeira Franco, Denis Correia de Vasconcelos, Mai Reliability fault tolerance combinational logic This paper deals with digital VLSI design aspects related to reliability. The focus is on the problem of reliability evaluation in combinational logic circuits.We present some methods for this evaluation that can be easily integrated in a tradidional design flow. Also we describe suitable metrics for performance estimation of concurrent error detection schemes. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Lirida Alves de Barros-Naviner and Jean-François Naviner and Denis Teixeira Franco and Mai Correia de Vasconcelos 2009 Is Part Of Dagstuhl Seminar Proceedings, Volume 8371, Fault-Tolerant Distributed Algorithms on VLSI Chips (2009) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/DagSemProc.08371.5 urn:nbn:de:0030-drops-19252 https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.08371.5 eng https://creativecommons.org/licenses/by/4.0/legalcode