2026-07-24T01:59:45Z https://drops.dagstuhl.de/oai

oai:drops-oai.dagstuhl.de:1926 2024-03-06T11:08:17Z ddc:004 open_access

Multiple Event Upsets Aware FPGAs Using Protected Schemes Argyrides, Costas Pradhan, Dhiraj K. FPGA SEUs ECC Reliability MTTF Multiple upsets would be available in SRAM-based FPGAs which utilizes SRAM in different parts to implement circuit configuration and to implement circuit data. Moreover, configuration bits of SRAM-based FPGAs are more sensible to upsets compared to circuit data due to significant number of SRAM bits. In this paper, a new protected Configurable Logic Block (CLB) and FPGA architecture are proposed which utilize multiple error correction (DEC) and multiple error detection. This is achieved by the incorporation of recently proposed coding technique Matrix codes [1] inside the FPGA. The power and area analysis of the proposed techniques show that these methods are more efficient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Costas Argyrides and Dhiraj K. Pradhan 2009 Is Part Of Dagstuhl Seminar Proceedings, Volume 8371, Fault-Tolerant Distributed Algorithms on VLSI Chips (2009) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/DagSemProc.08371.6 urn:nbn:de:0030-drops-19261 https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.08371.6 eng https://creativecommons.org/licenses/by/4.0/legalcode