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        <identifier>oai:drops-oai.dagstuhl.de:22207</identifier>
        <datestamp>2024-12-05T15:18:03Z</datestamp>
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          <dc:title>Circuits, Proofs and Propositional Model Counting</dc:title>
          <dc:creator>Chede, Sravanthi</dc:creator>
          <dc:creator>Chew, Leroy</dc:creator>
          <dc:creator>Shukla, Anil</dc:creator>
          <dc:subject>Propositional model counting</dc:subject>
          <dc:subject>Boolean circuits</dc:subject>
          <dc:subject>#SAT</dc:subject>
          <dc:subject>Proof Systems</dc:subject>
          <dc:subject>Certified Partition Operation Graph (CPOG)</dc:subject>
          <dc:description>In this paper we present a new proof system framework CLIP (Circuit Linear Induction Proposition) for propositional model counting (#SAT). A CLIP proof firstly involves a Boolean circuit, calculating the cumulative function (or running count) of models counted up to a point, and secondly a propositional proof arguing for the correctness of the circuit. &#13;
This concept is remarkably simple and CLIP is modular so it allows us to use existing checking formats from propositional logic, especially strong proof systems. CLIP has polynomial-size proofs for XOR-pairs which are known to require exponential-size proofs in MICE [Fichte et al., 2022]. The existence of a strong proof system that can tackle these hard problems was posed as an open problem in Beyersdorff et al. [Olaf Beyersdorff et al., 2023]. In addition, CLIP systems can p-simulate all other existing #SAT proofs systems (KCPS(#SAT) [Florent Capelli, 2019], CPOG [Bryant et al., 2023], MICE). Furthermore, CLIP has a theoretical advantage over the other #SAT proof systems in the sense that CLIP only has lower bounds from its propositional proof system or if 𝖯^#𝖯 is not contained in P/poly, which is a major open problem in circuit complexity. &#13;
CLIP uses unrestricted circuits in its proof as compared to restricted structures used by the existing #SAT proof systems. In this way, CLIP avoids hardness or limitations due to circuit restrictions.</dc:description>
          <dc:publisher>Schloss Dagstuhl – Leibniz-Zentrum für Informatik</dc:publisher>
          <dc:contributor>Sravanthi Chede and Leroy Chew and Anil Shukla</dc:contributor>
          <dc:date>2024</dc:date>
          <dc:relation>Is Part Of LIPIcs, Volume 323, 44th IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science (FSTTCS 2024)</dc:relation>
          <dc:type>InProceedings</dc:type>
          <dc:type>Text</dc:type>
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          <dc:identifier>doi:10.4230/LIPIcs.FSTTCS.2024.18</dc:identifier>
          <dc:identifier>urn:nbn:de:0030-drops-222079</dc:identifier>
          <dc:identifier>https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.FSTTCS.2024.18</dc:identifier>
          <dc:language>eng</dc:language>
          <dc:rights>https://creativecommons.org/licenses/by/4.0/legalcode</dc:rights>
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