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Is Chip-Multiprocessing the End of Real-Time Scheduling? Schoeberl, Martin Puschner, Peter WCET analysis multicore chip multiprocessing memory access scheduling Chip-multiprocessing is considered the future path for performance enhancements in computer architecture. Eight processor cores on a single chip are state-of-the art and several hundreds of cores on a single die are expected in the near future. General purpose computing is facing the challenge how to use the many cores. However, in embedded real-time systems thread-level parallelism is naturally used. In this paper we assume a system where we can dedicate a single core for each thread. In that case classic real-time scheduling disappears. However, the threads, running on their dedicated core, still compete for a shared resource, the main memory. A time-sliced memory arbiter is used to avoid timing influences between threads. The schedule of the arbiter is integrated into the worst-case execution time (WCET) analysis. The WCET results are used as a feedback to regenerate the arbiter schedule. Therefore, we schedule memory access instead of CPU time. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Martin Schoeberl and Peter Puschner 2009 Is Part Of OASIcs, Volume 10, 9th International Workshop on Worst-Case Execution Time Analysis (WCET'09) (2009) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/OASIcs.WCET.2009.2288 urn:nbn:de:0030-drops-22885 https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2009.2288 eng https://creativecommons.org/licenses/by-nc-nd/3.0/legalcode