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        <identifier>oai:drops-oai.dagstuhl.de:22907</identifier>
        <datestamp>2025-10-02T12:07:44Z</datestamp>
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          <dc:title>System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric</dc:title>
          <dc:creator>Muttillo, Vittoriano</dc:creator>
          <dc:creator>Stoico, Vincenzo</dc:creator>
          <dc:creator>Valente, Giacomo</dc:creator>
          <dc:creator>Santic, Marco</dc:creator>
          <dc:creator>Pomante, Luigi</dc:creator>
          <dc:creator>Frigioni, Daniele</dc:creator>
          <dc:subject>embedded systems</dc:subject>
          <dc:subject>hw/sw co-design</dc:subject>
          <dc:subject>performance estimation</dc:subject>
          <dc:subject>lasso</dc:subject>
          <dc:subject>machine learning</dc:subject>
          <dc:description>The rapidly increasing complexity of embedded systems and the critical impact of non-functional requirements demand the adoption of an appropriate system-level HW/SW co-design methodology. This methodology tries to satisfy all design requirements by simultaneously considering several alternative HW/SW implementations. In this context, early performance estimation approaches are crucial in reducing the design space, thereby minimizing design time and cost. To address the challenge of system-level performance estimation, this work presents and formalizes a novel approach based on a unifying HW/SW performance metric for early execution time estimation. The proposed approach estimates the execution time of a C function when executed by different HW/SW processor technologies. The approach is validated through an extensive experimental study, demonstrating its effectiveness and efficiency in terms of estimation error (i.e., lower than 10%) and estimation time (close to zero) when compared to existing methods in the literature.</dc:description>
          <dc:publisher>Schloss Dagstuhl – Leibniz-Zentrum für Informatik</dc:publisher>
          <dc:contributor>Vittoriano Muttillo and Vincenzo Stoico and Giacomo Valente and Marco Santic and Luigi Pomante and Daniele Frigioni</dc:contributor>
          <dc:date>2025</dc:date>
          <dc:relation>Is Part Of OASIcs, Volume 127, 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025)</dc:relation>
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          <dc:identifier>doi:10.4230/OASIcs.PARMA-DITAM.2025.3</dc:identifier>
          <dc:identifier>urn:nbn:de:0030-drops-229071</dc:identifier>
          <dc:identifier>https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2025.3</dc:identifier>
          <dc:language>eng</dc:language>
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