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Towards Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection Jeitler, Marcus Lechner, Jakob Four State Logic Asynchronous Design Fault Injection Fault Tolerance As transient error rates are growing due to smaller feature sizes, designing reliable synchronous circuits becomes increasingly challenging. Asynchronous logic design constitutes a promising alternative with respect to robustness and stability. In particular, delay-insensitive asynchronous circuits provide interesting properties, like an inherent resilience to delay-faults. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Marcus Jeitler and Jakob Lechner 2009 Is Part Of OASIcs, Volume 13, Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'09) (2009) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/DROPS.MEMICS.2009.2352 urn:nbn:de:0030-drops-23529 https://drops.dagstuhl.de/entities/document/10.4230/DROPS.MEMICS.2009.2352 eng https://creativecommons.org/licenses/by-nc-nd/3.0/legalcode