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Timing Anomalies Reloaded Gebhard, Gernot Timing Anomalies Domino Effects MRU Replacement Policy LEON2 Computing tight WCET bounds in the presence of timing anomalies - found in almost any modern hardware architecture - is a major challenge of timing analysis. In this paper, we renew the discussion about timing anomalies, demonstrating that even simple hardware architectures are prone to timing anomalies. We furthermore complete the list of timing-anomalous cache replacement policies, proving that the most-recently-used replacement policy (MRU) also exhibits a domino effect. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Gernot Gebhard 2010 Is Part Of OASIcs, Volume 15, 10th International Workshop on Worst-Case Execution Time Analysis (WCET 2010) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/OASIcs.WCET.2010.1 urn:nbn:de:0030-drops-28201 https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2010.1 eng https://creativecommons.org/licenses/by-nc-nd/3.0/legalcode