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oai:drops-oai.dagstuhl.de:2838 2024-03-06T11:09:22Z ddc:004 open_access

Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators Huthmann, Jens Müller, Peter Stock, Florian Hildenbrand, Dietmar Koch, Andreas Geometric Algebra FPGA High-Level-Compiler Gaalop Geometric Algebra (GA), a generalization of quaternions and complex numbers, is a very powerful framework for intuitively expressing and manipulating the complex geometric relationships common to engineering problems. However, actual processing of GA expressions is very compute intensive, and acceleration is generally required for practical use. GPUs and FPGAs offer such acceleration, while requiring only low-power per operation. In this paper, we present key components of a proof-of-concept compile flow combining symbolic and hardware optimization techniques to automatically generate hardware accelerators from the abstract GA descriptions that are suitable for high-performance embedded computing. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Jens Huthmann and Peter Müller and Florian Stock and Dietmar Hildenbrand and Andreas Koch 2010 Is Part Of Dagstuhl Seminar Proceedings, Volume 10281, Dynamically Reconfigurable Architectures (2010) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/DagSemProc.10281.6 urn:nbn:de:0030-drops-28389 https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.6 eng https://creativecommons.org/licenses/by/4.0/legalcode