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The Optimization of Interconnection Networks in FPGAs Chen, Xiaolei Ha, Yajun Field-programmable gate array architecture computer-aided design Scaling technology enables even higher degree of integration for FPGAs, but also brings new challenges that need to be addressed from both the architecture and the design tools side. Optimization of FPGA interconnection network is essential, given that interconnects dominate logic. Two approaches are presented, with one based on the time-multiplexing of wires and the other using hierarchical interconnects of high-speed serial links and switches. Design tools for both approaches are discussed. Preliminary experiments and prototypes are presented, and show positive results. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Xiaolei Chen and Yajun Ha 2010 Is Part Of Dagstuhl Seminar Proceedings, Volume 10281, Dynamically Reconfigurable Architectures (2010) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/DagSemProc.10281.12 urn:nbn:de:0030-drops-28425 https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.12 eng https://creativecommons.org/licenses/by/4.0/legalcode