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        <identifier>oai:drops-oai.dagstuhl.de:306</identifier>
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          <dc:title>Methodologies for Designing Power-Aware Smart Card Systems</dc:title>
          <dc:creator>Steger, Christian</dc:creator>
          <dc:creator>Neffe, Ulrich</dc:creator>
          <dc:creator>Rothbart, Klaus</dc:creator>
          <dc:creator>Mühlberger, Andreas</dc:creator>
          <dc:creator>Rieger, Edgar</dc:creator>
          <dc:creator>Weiss, Reinhold</dc:creator>
          <dc:subject>Smart cards</dc:subject>
          <dc:subject>power awareness</dc:subject>
          <dc:subject>HW/SW codesign</dc:subject>
          <dc:subject>cycle-accurate instruction-set simulator</dc:subject>
          <dc:description>Smart cards are some of the smallest &#13;
computing platforms in use today. They have &#13;
limited resources, but a huge number of &#13;
functional requirements. The requirement for &#13;
multi-application cards increases the demand &#13;
for high performance and security even more, &#13;
whereas the limits given by size and energy &#13;
consumption remain constant. &#13;
&#13;
We describe  new &#13;
methodologies for designing and implementing &#13;
entire systems with regard to power awareness &#13;
and required performance. To make use of this &#13;
power-saving potential, also the higher layers &#13;
of the system - the operating system layer and &#13;
the application domain layer - are required to &#13;
be designed together with the rest of the &#13;
system.&#13;
&#13;
HW/SW co-design methodologies enable the gain of &#13;
system-level optimization. The first part  presents the &#13;
abstraction of smart cards to optimize system architecture &#13;
and memory system. Both functional and transactional-level &#13;
models are presented and discussed. The proposed design &#13;
flow and preliminary results of the evaluation are depicted.&#13;
&#13;
Another central part of this methodology  is a cycle-accurate instruction-set&#13;
simulator for secure software development. &#13;
The underlaying energy model is designed&#13;
to decouple instruction and data dependent energy dissipation,&#13;
which leads to an independent characterization process and allows&#13;
stepwise model refinement to increase estimation accuracy. The&#13;
model has been evaluated for a high-performance smart card CPU and&#13;
an use-case for secure software is given.</dc:description>
          <dc:publisher>Schloss Dagstuhl – Leibniz-Zentrum für Informatik</dc:publisher>
          <dc:contributor>Christian Steger and Ulrich Neffe and Klaus Rothbart and Andreas Mühlberger and Edgar Rieger and Reinhold Weiss</dc:contributor>
          <dc:date>2005</dc:date>
          <dc:relation>Is Part Of Dagstuhl Seminar Proceedings, Volume 5141, Power-aware Computing Systems (2005)</dc:relation>
          <dc:type>InProceedings</dc:type>
          <dc:type>Text</dc:type>
          <dc:type>doc-type:ResearchArticle</dc:type>
          <dc:type>publishedVersion</dc:type>
          <dc:format>application/pdf</dc:format>
          <dc:identifier>doi:10.4230/DagSemProc.05141.7</dc:identifier>
          <dc:identifier>urn:nbn:de:0030-drops-3067</dc:identifier>
          <dc:identifier>https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05141.7</dc:identifier>
          <dc:language>eng</dc:language>
          <dc:rights>https://creativecommons.org/licenses/by/4.0/legalcode</dc:rights>
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