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          <dc:title>Instructor Selector Generation from Architecture Description</dc:title>
          <dc:creator>Trmac, Miloslav</dc:creator>
          <dc:creator>Husar, Adam</dc:creator>
          <dc:creator>Hranac, Jan</dc:creator>
          <dc:creator>Hruska, Tomas</dc:creator>
          <dc:creator>Masarik, Karel</dc:creator>
          <dc:subject>LLVM</dc:subject>
          <dc:subject>instruction generator</dc:subject>
          <dc:description>We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer level.&#13;
The generated instruction selector can handle arbitrarily complex machine instructions with no internal control flow, and can automatically find and take advantage of arithmetic properties of an instructions, specialized pseudo-registers and special cases of immediate operands.</dc:description>
          <dc:publisher>Schloss Dagstuhl – Leibniz-Zentrum für Informatik</dc:publisher>
          <dc:contributor>Miloslav Trmac and Adam Husar and Jan Hranac and Tomas Hruska and Karel Masarik</dc:contributor>
          <dc:date>2011</dc:date>
          <dc:relation>Is Part Of OASIcs, Volume 16, Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers (2011)</dc:relation>
          <dc:type>InProceedings</dc:type>
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          <dc:identifier>doi:10.4230/OASIcs.MEMICS.2010.109</dc:identifier>
          <dc:identifier>urn:nbn:de:0030-drops-30616</dc:identifier>
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