2026-07-21T14:19:01Z https://drops.dagstuhl.de/oai

oai:drops-oai.dagstuhl.de:3077 2024-03-06T10:28:52Z ddc:004 open_access

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach Schoeberl, Martin Schleuniger, Pascal Puffitsch, Wolfgang Brandner, Florian Probst, Christian W. Time-predictable architecture WCET analysis WCET-aware compilation Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual-issue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Martin Schoeberl and Pascal Schleuniger and Wolfgang Puffitsch and Florian Brandner and Christian W. Probst 2011 Is Part Of OASIcs, Volume 18, Bringing Theory to Practice: Predictability and Performance in Embedded Systems (2011) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/OASIcs.PPES.2011.11 urn:nbn:de:0030-drops-30774 https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PPES.2011.11 eng https://creativecommons.org/licenses/by-nd/3.0/legalcode