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Requirements for and Design of a Processor with Predictable Timing Berg, Christoph Engblom, Jakob Wilhelm, Reinhard WCET hard real-time embedded systems computer architecture This paper introduces a set of design principles that aim to make processor architectures amenable to static timing analysis. Based on these principles, we give a design of a hard real-time processor with predictable timing, which is simultaneously capable of reaching respectable performance levels. The design principles we identify are recoverability from information loss in the analysis, minimal variation of the instruction timing, non-interference between processor components, deterministic processor behavior, and comprehensive documentation. The principles are based on our experience and that of other researchers in building timing analysis tools for existing processors. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Christoph Berg and Jakob Engblom and Reinhard Wilhelm 2004 Is Part Of Dagstuhl Seminar Proceedings, Volume 3471, Perspectives Workshop: Design of Systems with Predictable Behaviour (2004) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/DagSemProc.03471.4 urn:nbn:de:0030-drops-57 https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.03471.4 eng https://creativecommons.org/licenses/by/4.0/legalcode