2026-07-20T05:42:10Z https://drops.dagstuhl.de/oai

oai:drops-oai.dagstuhl.de:5252 2024-03-06T10:29:47Z ddc:004 open_access

Software-enforced Interconnect Arbitration for COTS Multicores Ziccardi, Marco Cornaglia, Alessandro Mezzetti, Enrico Vardanega, Tullio Multicore Resource Arbitration Interference Mixed-Criticality The advent of multicore processors complicates timing analysis owing to the need to account for the interference between cores accessing shared resources, which is not always easy to characterize in a safe and tight way. Solutions have been proposed that take two distinct but complementary directions: on the one hand, complex analysis techniques have been developed to provide safe and tight bounds to contention; on the other hand, sophisticated arbitration policies (hardware or software) have been proposed to limit or control inter-core interference. In this paper we propose a software-based TDMA-like arbitration of accesses to a shared interconnect (e.g. a bus) that prevents inter-core interference. A more flexible arbitration scheme is also proposed to reserve more bandwidth to selected cores while still avoiding contention. A proof-of-concept implementation on an AURIX TC277TU processor shows that our approach can apply to COTS processors, thus not relying on dedicated hardware arbiters, while introducing little overhead. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Marco Ziccardi and Alessandro Cornaglia and Enrico Mezzetti and Tullio Vardanega 2015 Is Part Of OASIcs, Volume 47, 15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/OASIcs.WCET.2015.11 urn:nbn:de:0030-drops-52526 https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2015.11 eng https://creativecommons.org/licenses/by/3.0/legalcode