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        <identifier>oai:drops-oai.dagstuhl.de:672</identifier>
        <datestamp>2024-03-06T10:28:24Z</datestamp>
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          <dc:title>PLRU Cache Domino Effects</dc:title>
          <dc:creator>Berg, Christoph</dc:creator>
          <dc:subject>Embedded systems</dc:subject>
          <dc:subject>predictability</dc:subject>
          <dc:subject>cache memory</dc:subject>
          <dc:subject>PLRU</dc:subject>
          <dc:subject>domino effects</dc:subject>
          <dc:subject>timing anomalies</dc:subject>
          <dc:description>Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and StenstrÃƒÂ¶m, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models.</dc:description>
          <dc:publisher>Schloss Dagstuhl – Leibniz-Zentrum für Informatik</dc:publisher>
          <dc:contributor>Christoph Berg</dc:contributor>
          <dc:date>2006</dc:date>
          <dc:relation>Is Part Of OASIcs, Volume 4, 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06) (2006)</dc:relation>
          <dc:type>InProceedings</dc:type>
          <dc:type>Text</dc:type>
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          <dc:identifier>doi:10.4230/OASIcs.WCET.2006.672</dc:identifier>
          <dc:identifier>urn:nbn:de:0030-drops-6723</dc:identifier>
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          <dc:language>eng</dc:language>
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