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        <datestamp>2024-03-06T10:39:52Z</datestamp>
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          <dc:title>WCET Derivation under Single Core Equivalence with Explicit Memory Budget Assignment</dc:title>
          <dc:creator>Mancuso, Renato</dc:creator>
          <dc:creator>Pellizzoni, Rodolfo</dc:creator>
          <dc:creator>Tokcan, Neriman</dc:creator>
          <dc:creator>Caccamo, Marco</dc:creator>
          <dc:subject>real-time multicore</dc:subject>
          <dc:subject>WCET</dc:subject>
          <dc:subject>single-core equivalence</dc:subject>
          <dc:subject>DRAM management</dc:subject>
          <dc:subject>certification</dc:subject>
          <dc:description>In the last decade there has been a steady uptrend in the popularity of embedded multi-core platforms. This represents a turning point in the theory and implementation of real-time systems. From a real-time standpoint, however, the extensive sharing of hardware resources (e.g. caches, DRAM subsystem, I/O channels) represents a major source of unpredictability. Budget-based memory regulation (throttling) has been extensively studied to enforce a strict partitioning of the DRAM subsystem’s bandwidth. The common approach to analyze a task under memory bandwidth regulation is to consider the budget of the core where the task is executing, and assume the worst-case about the remaining cores' budgets.&#13;
&#13;
In this work, we propose a novel analysis strategy to derive the WCET of a task under memory bandwidth regulation that takes into account the exact distribution of memory budgets to cores. In this sense, the proposed analysis represents a generalization of approaches that consider (i) even budget distribution across cores; and (ii) uneven but unknown (except for the core under analysis) budget assignment. By exploiting the additional piece of information, we show that it is possible to derive a more accurate WCET estimation. Our evaluations highlight that the proposed technique can reduce overestimation by 30% in average, and up to 60%, compared to the state of the art.</dc:description>
          <dc:publisher>Schloss Dagstuhl – Leibniz-Zentrum für Informatik</dc:publisher>
          <dc:contributor>Renato Mancuso and Rodolfo Pellizzoni and Neriman Tokcan and Marco Caccamo</dc:contributor>
          <dc:date>2017</dc:date>
          <dc:relation>Is Part Of LIPIcs, Volume 76, 29th Euromicro Conference on Real-Time Systems (ECRTS 2017)</dc:relation>
          <dc:type>InProceedings</dc:type>
          <dc:type>Text</dc:type>
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          <dc:identifier>doi:10.4230/LIPIcs.ECRTS.2017.3</dc:identifier>
          <dc:identifier>urn:nbn:de:0030-drops-71684</dc:identifier>
          <dc:identifier>https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.3</dc:identifier>
          <dc:language>eng</dc:language>
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