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Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System Maskell, Douglas Oliver, Timothy F. Dynamic Reconfiguration Rapid Construction FPGA Routing matrix This paper presents a method of constructing pre-routed FPGA cores. This lays the foundations for a rapid system construction framework. There are two major challenges that need to be considered by this framework. The first is how to manage the wires crossing a core’s borders. The second is how to maintain an acceptable level of flexibility for system construction with only a minimum of overhead. Typical FPGA based systems are built up from cores developed by multiple third parties. Each compilation step that a developer performs before delivery adds value in terms of a cores performance, predictability and readiness for purpose. The perceived advantages of full independent core development are weighed against the loss in placement flexibility and elimination of the opportunities to optimise a system across cores. Few existing methodologies allow the independent compilation of FPGA cores through every step of the design flow. The wire detail of modern FPGA architectures is captured in a model that is used to analyse how the interconnect architecture effects the shape of pre-routed cores and the wire bandwidth available to interfaces. We have adapted academic placement and routing algorithms to our architectural model. The design flow has been modified to include a wire policy and interface constraints framework that tightly constrains the use of the wires that cross a core’s boundaries. Using this tool set we investigate the effect of pre-routing on overall system optimality. Compiling a set of example systems using the pre-routed approach shows only a 2% increase in total wire use over the pre-placed approach. Place and route times are vastly reduced for systems composed of regular modules. Being able to break a system into independent cores reduces the placement and routing time even for non-regular systems, and will open opportunities for its possible use in resource constrained embedded systems. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Douglas Maskell and Timothy F. Oliver 2006 Is Part Of Dagstuhl Seminar Proceedings, Volume 6141, Dynamically Reconfigurable Architectures (2006) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/DagSemProc.06141.12 urn:nbn:de:0030-drops-7410 https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.12 eng https://creativecommons.org/licenses/by/4.0/legalcode