2026-07-23T07:56:15Z https://drops.dagstuhl.de/oai

oai:drops-oai.dagstuhl.de:813 2024-03-06T10:28:18Z ddc:004 open_access

Analysis of Memory Latencies in Multi-Processor Systems Stachulat, Jan Schliecker, Simon Ivers, Matthias Ernst, Rolf Multi-processor Performance Analysis Memory Access Latency Worst Case Execution Time Predicting timing behavior is key to efficient embedded real-time system design and verification. Current approaches to determine end-to-end latencies in parallel heterogeneous architectures focus on performance analysis either on task or system level. Especially memory accesses, basic operations of embedded application, cannot be accurately captured on a single level alone: While task level methods simplify system behavior, system level methods simplify task behavior. Both perspectives lead to overly pessimistic estimations. To tackle these complex interactions we integrate task and system level analysis. Each analysis level is provided with the necessary data to allow precise computations, while adequate abstraction prevents high time complexity. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Jan Stachulat and Simon Schliecker and Matthias Ivers and Rolf Ernst 2007 Is Part Of OASIcs, Volume 1, 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05) (2007) InProceedings Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/OASIcs.WCET.2005.813 urn:nbn:de:0030-drops-8130 https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2005.813 eng https://creativecommons.org/licenses/by-nc-nd/3.0/legalcode