2026-07-20T05:59:59Z https://drops.dagstuhl.de/oai

oai:drops-oai.dagstuhl.de:8973 2024-03-06T11:05:03Z ddc:004 open_access

Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact) Awan, Muhammad Ali Souto, Pedro F. Bletsas, Konstantinos Akesson, Benny Tovar, Eduardo multiple memory controllers memory regulation multicore This artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform. Schloss Dagstuhl – Leibniz-Zentrum für Informatik Muhammad Ali Awan and Pedro F. Souto and Konstantinos Bletsas and Benny Akesson and Eduardo Tovar 2018 Is Part Of DARTS, Volume 4, Issue 2, Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018) Article Text doc-type:ResearchArticle publishedVersion application/pdf doi:10.4230/DARTS.4.2.5 urn:nbn:de:0030-drops-89732 https://drops.dagstuhl.de/entities/document/10.4230/DARTS.4.2.5 eng https://creativecommons.org/licenses/by/3.0/de/legalcode