| No. |
Title |
Author |
Year |
| 1 |
Front Matter, Table of Contents, Preface, Conference Organization |
Papadopoulos, Alessandro V. et al. |
2020 |
| 2 |
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs |
Restuccia, Francesco et al. |
2020 |
| 3 |
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact) |
Restuccia, Francesco et al. |
2020 |
| 4 |
A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs |
Pagani, Marco et al. |
2019 |
| 5 |
Beyond the Weakly Hard Model: Measuring the Performance Cost of Deadline Misses |
Pazzaglia, Paolo et al. |
2018 |
| 6 |
Beyond the Weakly Hard Model: Measuring the Performance Cost of Deadline Misses (Artifact) |
Pazzaglia, Paolo et al. |
2018 |
| 7 |
Semi-Partitioned Scheduling of Dynamic Real-Time Workload: A Practical Approach Based on Analysis-Driven Load Balancing |
Casini, Daniel et al. |
2017 |
