No. Title Author Year
1 Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs Restuccia, Francesco et al. 2020
2 Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact) Restuccia, Francesco et al. 2020
3 A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs Pagani, Marco et al. 2019
4 Semi-Partitioned Scheduling of Dynamic Real-Time Workload: A Practical Approach Based on Analysis-Driven Load Balancing Casini, Daniel et al. 2017
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