5 Search Results for "González-Ortega, David"

Document
DOI: 10.4230/OASIcs.WCET.2023.3
Exploring iGPU Memory Interference Response to L2 Cache Locking

Authors: Alfonso Mascareñas González, Jean-Baptiste Chaudron, Régine Leconte, Youcef Bouchebaba, and David Doose

Published in: OASIcs, Volume 114, 21th International Workshop on Worst-Case Execution Time Analysis (WCET 2023)

Abstract
The demand of parallel execution in real-time embedded applications has motivated the integration of GPUs as processing accelerators on SoCs (System-on-Chip) embedded architectures, often leading to CPU-iGPU architectures. In the safety-critical domain, it is paramount to ensure that the execution deadlines of critical tasks are not exceeded. To ease the analysis of this kind of tasks, we can make their worst-case execution time more predictable. One way to achieve this is by mitigating or controlling the memory interference generated by the concurrent execution of tasks through the application of a series of techniques (e.g., cache partitioning, bank partitioning, cache locking, bandwidth regulation). Originally, these were applied to CPUs, and more recently, to GPUs as well. In this work, we focus on the hardware-based L2 cache locking on iGPUs as memory interference mitigation mechanism. We are interested in evaluating its capacity for reducing the worst-case and the average-case execution time in different scenarios. Our measurement-based analysis has been carried out on the NVIDIA’s Jetson AGX Orin 64 GB MPSoC, making use of four representative benchmarks (data resetting, 2D convolution, 3D convolution and matrix upsampling).
Cite as

Alfonso Mascareñas González, Jean-Baptiste Chaudron, Régine Leconte, Youcef Bouchebaba, and David Doose. Exploring iGPU Memory Interference Response to L2 Cache Locking. In 21th International Workshop on Worst-Case Execution Time Analysis (WCET 2023). Open Access Series in Informatics (OASIcs), Volume 114, pp. 3:1-3:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

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@InProceedings{gonzalez_et_al:OASIcs.WCET.2023.3,
  author =	{Gonz\'{a}lez, Alfonso Mascare\~{n}as and Chaudron, Jean-Baptiste and Leconte, R\'{e}gine and Bouchebaba, Youcef and Doose, David},
  title =	{{Exploring iGPU Memory Interference Response to L2 Cache Locking}},
  booktitle =	{21th International Workshop on Worst-Case Execution Time Analysis (WCET 2023)},
  pages =	{3:1--3:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-293-8},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{114},
  editor =	{W\"{a}gemann, Peter},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2023.3},
  URN =		{urn:nbn:de:0030-drops-184321},
  doi =		{10.4230/OASIcs.WCET.2023.3},
  annote =	{Keywords: iGPU, cache locking, real-time, memory interference}
}
Document
DOI: 10.4230/LIPIcs.ISAAC.2022.31
Locally Checkable Problems Parameterized by Clique-Width

Authors: Narmina Baghirova, Carolina Lucía Gonzalez, Bernard Ries, and David Schindl

Published in: LIPIcs, Volume 248, 33rd International Symposium on Algorithms and Computation (ISAAC 2022)

Abstract
We continue the study initiated by Bonomo-Braberman and Gonzalez in 2020 on r-locally checkable problems. We propose a dynamic programming algorithm that takes as input a graph with an associated clique-width expression and solves a 1-locally checkable problem under certain restrictions. We show that it runs in polynomial time in graphs of bounded clique-width, when the number of colors of the locally checkable problem is fixed. Furthermore, we present a first extension of our framework to global properties by taking into account the sizes of the color classes, and consequently enlarge the set of problems solvable in polynomial time with our approach in graphs of bounded clique-width. As examples, we apply this setting to show that, when parameterized by clique-width, the [k]-Roman domination problem is FPT, and the k-community problem, Max PDS and other variants are XP.
Cite as

Narmina Baghirova, Carolina Lucía Gonzalez, Bernard Ries, and David Schindl. Locally Checkable Problems Parameterized by Clique-Width. In 33rd International Symposium on Algorithms and Computation (ISAAC 2022). Leibniz International Proceedings in Informatics (LIPIcs), Volume 248, pp. 31:1-31:20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022)

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@InProceedings{baghirova_et_al:LIPIcs.ISAAC.2022.31,
  author =	{Baghirova, Narmina and Gonzalez, Carolina Luc{\'\i}a and Ries, Bernard and Schindl, David},
  title =	{{Locally Checkable Problems Parameterized by Clique-Width}},
  booktitle =	{33rd International Symposium on Algorithms and Computation (ISAAC 2022)},
  pages =	{31:1--31:20},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-258-7},
  ISSN =	{1868-8969},
  year =	{2022},
  volume =	{248},
  editor =	{Bae, Sang Won and Park, Heejin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ISAAC.2022.31},
  URN =		{urn:nbn:de:0030-drops-173167},
  doi =		{10.4230/LIPIcs.ISAAC.2022.31},
  annote =	{Keywords: locally checkable problem, clique-width, dynamic programming, coloring}
}
Document
DOI: 10.4230/OASIcs.NG-RES.2021.5
M2OS-Mc: An RTOS for Many-Core Processors

Authors: David García Villaescusa, Mario Aldea Rivas, and Michael González Harbour

Published in: OASIcs, Volume 87, Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)

Abstract
A current trend of industrial systems is reducing space, weight and power (SWaP) through the allocation of different applications on a single chip. This is enabled by the continued improvement of semiconductor technology which allows the integration of multiple cores in a single processor chip, as the processors are prevented to continue increasing their clock rate due to the "power-wall". The use of Commercial-Off-The-Shelf (COTS) multi-core processors for real-time purposes presents issues due to the shared bus used to access the shared memory. An alternative to the use of multi-core processors are the many-core processors with tens to hundreds of processors in the same chip, using different scalable ways to interconnect their cores. This paper presents the adaptation of the M2OS Real-Time Operating System (RTOS) and its simplified Ada run-time for mesh-based many-core processors. This RTOS is called M2OS-mc and has been tested on the Epiphany III many-core processor (referred in this paper simply as Epiphany), a many-core which has 16 cores connected by a Network-on-Chip (NoC) consisting of a 4x4 2D mesh. In order to have a synchronized way to send messages between tasks through the NoC independently of the core where they are being executed, we provide sampling port communication primitives.
Cite as

David García Villaescusa, Mario Aldea Rivas, and Michael González Harbour. M2OS-Mc: An RTOS for Many-Core Processors. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 5:1-5:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)

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@InProceedings{villaescusa_et_al:OASIcs.NG-RES.2021.5,
  author =	{Villaescusa, David Garc{\'\i}a and Rivas, Mario Aldea and Harbour, Michael Gonz\'{a}lez},
  title =	{{M2OS-Mc: An RTOS for Many-Core Processors}},
  booktitle =	{Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
  pages =	{5:1--5:13},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-178-8},
  ISSN =	{2190-6807},
  year =	{2021},
  volume =	{87},
  editor =	{Bertogna, Marko and Terraneo, Federico},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.5},
  URN =		{urn:nbn:de:0030-drops-134814},
  doi =		{10.4230/OASIcs.NG-RES.2021.5},
  annote =	{Keywords: M2OS, Many-Core, Real-Time, Parallella, Epiphany, Network-on-Chip, Operating System, RTOS}
}
Document
DOI: 10.4230/OASIcs.ICPEC.2020.3
An Experience of Game-Based Learning in Web Applications Development Courses

Authors: Míriam Antón-Rodríguez, María Ángeles Pérez-Juárez, Francisco Javier Díaz-Pernas, David González-Ortega, Mario Martínez-Zarzuela, and Javier Manuel Aguiar-Pérez

Published in: OASIcs, Volume 81, First International Computer Programming Education Conference (ICPEC 2020)

Abstract
Preparing graduates for working in the software engineering industry is challenging and requires effective learning frameworks and methodologies. More specifically, the challenge of teaching programming languages and paradigms is a very complex task that needs innovative educational tools. This paper presents a game-based educational tool named eLiza, developed and used to support the teaching and learning of programming languages and paradigms related to the development of web applications. eLiza was initially developed as a Moodle-based web application because Moodle is the educational eLearning platform used at the University of Valladolid, but as the use of mobile devices is constantly increasing, Android and iOS versions were created later in order to facilitate the access of the students to the games. This paper describes the main elements and the mechanics in playing eLiza. And it also describes an experience of its use in two engineering courses related to web programming applications development, offered to students in two different engineering study programs at the University of Valladolid, during the academic years 2017-2018 and 2018-2019. The great majority of the students, more than 75%, considered that the use of the eLiza game-based educational tool was positive to improve the teaching and learning process of the topics covered by the courses.
Cite as

Míriam Antón-Rodríguez, María Ángeles Pérez-Juárez, Francisco Javier Díaz-Pernas, David González-Ortega, Mario Martínez-Zarzuela, and Javier Manuel Aguiar-Pérez. An Experience of Game-Based Learning in Web Applications Development Courses. In First International Computer Programming Education Conference (ICPEC 2020). Open Access Series in Informatics (OASIcs), Volume 81, pp. 3:1-3:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)

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@InProceedings{antonrodriguez_et_al:OASIcs.ICPEC.2020.3,
  author =	{Ant\'{o}n-Rodr{\'\i}guez, M{\'\i}riam and P\'{e}rez-Ju\'{a}rez, Mar{\'\i}a \'{A}ngeles and D{\'\i}az-Pernas, Francisco Javier and Gonz\'{a}lez-Ortega, David and Mart{\'\i}nez-Zarzuela, Mario and Aguiar-P\'{e}rez, Javier Manuel},
  title =	{{An Experience of Game-Based Learning in Web Applications Development Courses}},
  booktitle =	{First International Computer Programming Education Conference (ICPEC 2020)},
  pages =	{3:1--3:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-153-5},
  ISSN =	{2190-6807},
  year =	{2020},
  volume =	{81},
  editor =	{Queir\'{o}s, Ricardo and Portela, Filipe and Pinto, M\'{a}rio and Sim\~{o}es, Alberto},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.ICPEC.2020.3},
  URN =		{urn:nbn:de:0030-drops-122901},
  doi =		{10.4230/OASIcs.ICPEC.2020.3},
  annote =	{Keywords: eLearning, mLearning, Game-based Learning, Programming Languages, Web Applications Development}
}
Document
DOI: 10.4230/LIPIcs.TIME.2019.6
The Second Order Traffic Fine: Temporal Reasoning in European Transport Regulations

Authors: Ana de Almeida Borges, Juan José Conejero Rodríguez, David Fernández-Duque, Mireia González Bedmar, and Joost J. Joosten

Published in: LIPIcs, Volume 147, 26th International Symposium on Temporal Representation and Reasoning (TIME 2019)

Abstract
We argue that European transport regulations can be formalized within the Sigma^1_1 fragment of monadic second order logic, and possibly weaker fragments including linear temporal logic. We consider several articles in the regulation to verify these claims.
Cite as

Ana de Almeida Borges, Juan José Conejero Rodríguez, David Fernández-Duque, Mireia González Bedmar, and Joost J. Joosten. The Second Order Traffic Fine: Temporal Reasoning in European Transport Regulations. In 26th International Symposium on Temporal Representation and Reasoning (TIME 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 147, pp. 6:1-6:16, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{dealmeidaborges_et_al:LIPIcs.TIME.2019.6,
  author =	{de Almeida Borges, Ana and Conejero Rodr{\'\i}guez, Juan Jos\'{e} and Fern\'{a}ndez-Duque, David and Gonz\'{a}lez Bedmar, Mireia and Joosten, Joost J.},
  title =	{{The Second Order Traffic Fine: Temporal Reasoning in European Transport Regulations}},
  booktitle =	{26th International Symposium on Temporal Representation and Reasoning (TIME 2019)},
  pages =	{6:1--6:16},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-127-6},
  ISSN =	{1868-8969},
  year =	{2019},
  volume =	{147},
  editor =	{Gamper, Johann and Pinchinat, Sophie and Sciavicco, Guido},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.TIME.2019.6},
  URN =		{urn:nbn:de:0030-drops-113649},
  doi =		{10.4230/LIPIcs.TIME.2019.6},
  annote =	{Keywords: linear temporal logic, monadic second order logic, formalized law, transport regulations}
}
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