2 Search Results for "Hossam, Mohamed"

Document
DOI: 10.4230/LIPIcs.ECRTS.2023.17
A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources

Authors: Shorouk Abdelhalim, Danesh Germchi, Mohamed Hossam, Rodolfo Pellizzoni, and Mohamed Hassan

Published in: LIPIcs, Volume 262, 35th Euromicro Conference on Real-Time Systems (ECRTS 2023)

Abstract
To facilitate the safe adoption of multi-core platforms in real-time systems, a plethora of recent research efforts aim at bounding the delays induced by interference upon accessing the shared memory resources in these platforms. These efforts, despite their value, are scattered, with each one focusing solely on only one of these resources with the premise that latency bounds separately driven for each resource can be added all together to provide a safe end-to-end memory bound. In this work, we put this assumption to the test for the first time by 1) considering a realistic multi-core memory hierarchy system, 2) deriving the bounds for accessing the shared resources in this system, and 3) highlighting the limitations of this widely-adopted approach. In particular, we show that this approach leads to not only excessively pessimistic but also unsafe bounds. Motivated by these findings, we propose GRROF: a novel approach to predictably and efficiently schedule memory requests while traversing the entire memory hierarchy through coordination among arbiters managing all the resources in this hierarchy. By virtue of this novel mechanism, we managed to exploit pipelining upon analyzing the latency of the memory requests for tightly bounding the worst-case latency. We prove in the paper that GRROF enables us to derive a drastically tighter bound compared to the common additive latency approach with more than 18× reduction in the end-to-end memory latency bound for a modern Out-of-Order quad-core platform. The reduction is further improved significantly with the increase in the number of cores. The proposed solution is fully prototyped and tested in a cycle-accurate simulation. We also compare it with real-time competitive state-of-the-art and performance-oriented solutions existing in modern Commercial-off-the-Shelf (COTS) platforms.
Cite as

Shorouk Abdelhalim, Danesh Germchi, Mohamed Hossam, Rodolfo Pellizzoni, and Mohamed Hassan. A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources. In 35th Euromicro Conference on Real-Time Systems (ECRTS 2023). Leibniz International Proceedings in Informatics (LIPIcs), Volume 262, pp. 17:1-17:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

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@InProceedings{abdelhalim_et_al:LIPIcs.ECRTS.2023.17,
  author =	{Abdelhalim, Shorouk and Germchi, Danesh and Hossam, Mohamed and Pellizzoni, Rodolfo and Hassan, Mohamed},
  title =	{{A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources}},
  booktitle =	{35th Euromicro Conference on Real-Time Systems (ECRTS 2023)},
  pages =	{17:1--17:25},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-280-8},
  ISSN =	{1868-8969},
  year =	{2023},
  volume =	{262},
  editor =	{Papadopoulos, Alessandro V.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2023.17},
  URN =		{urn:nbn:de:0030-drops-180463},
  doi =		{10.4230/LIPIcs.ECRTS.2023.17},
  annote =	{Keywords: Predictability, Main Memory, Caches, Real-time}
}
Document
DOI: 10.4230/LIPIcs.ECRTS.2022.17
Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems

Authors: Mohamed Hossam and Mohamed Hassan

Published in: LIPIcs, Volume 231, 34th Euromicro Conference on Real-Time Systems (ECRTS 2022)

Abstract
The adoption of multi-core platforms in embedded real-time systems mandates predictable system components. Such components must guarantee the satisfaction of the timing constraints of various applications running on the system. One of the components that can break the system predictability is cache coherence, which ensures the correctness of shared data. This paper proposes a solution towards the enablement of predictable cache coherent real-time systems. The solution uses existing COTS coherence protocols and proposes a methodology to integrate them with legacy real-time arbiters without imposing any required modification to either of them. Doing so, the paper also works as an exploratory study of the integration of various coherence protocols with various predictable arbitration schemes leading to a total of 12 different architecture configurations. Evaluation against four state-of-the-art predictable coherence solutions as well as COTS-based solutions show that the proposed approach achieves the tightest existing latency bounds among predictable solutions with minimal performance degradation over the COTS ones.
Cite as

Mohamed Hossam and Mohamed Hassan. Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems. In 34th Euromicro Conference on Real-Time Systems (ECRTS 2022). Leibniz International Proceedings in Informatics (LIPIcs), Volume 231, pp. 17:1-17:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022)

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@InProceedings{hossam_et_al:LIPIcs.ECRTS.2022.17,
  author =	{Hossam, Mohamed and Hassan, Mohamed},
  title =	{{Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems}},
  booktitle =	{34th Euromicro Conference on Real-Time Systems (ECRTS 2022)},
  pages =	{17:1--17:23},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-239-6},
  ISSN =	{1868-8969},
  year =	{2022},
  volume =	{231},
  editor =	{Maggio, Martina},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2022.17},
  URN =		{urn:nbn:de:0030-drops-163345},
  doi =		{10.4230/LIPIcs.ECRTS.2022.17},
  annote =	{Keywords: Coherence, Shared Data, Caches, Multi-Core, Real-Time, Memory}
}
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