| No. |
Title |
Author |
Year |
| 1 |
Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation |
Platzer, Michael et al. |
2021 |
| 2 |
Best Practice for Caching of Single-Path Code |
Schoeberl, Martin et al. |
2017 |
| 3 |
Towards Automated Generation of Time-Predictable Code |
Prokesch, Daniel et al. |
2014 |
| 4 |
Improving System-Level Verification of SystemC Models with SPIN |
Elshuber, Martin et al. |
2013 |
| 5 |
A Formal Framework for Precise Parametric WCET Formulas |
Huber, Benedikt et al. |
2012 |
| 6 |
A Code Policy Guaranteeing Fully Automated Path Analysis |
Huber, Benedikt et al. |
2010 |
| 7 |
Is Chip-Multiprocessing the End of Real-Time Scheduling? |
Schoeberl, Martin et al. |
2009 |
| 8 |
Teaching WCET Analysis in Academia and Industry: A Panel Discussion |
Holsti, Niklas et al. |
2009 |
| 9 |
On Composable System Timing, Task Timing, and WCET Analysis |
Puschner, Peter et al. |
2008 |
| 10 |
Classification of Code Annotations and Discussion of Compiler-Support for Worst-Case Execution Time Analysis |
Kirner, Raimund et al. |
2007 |
| 11 |
Comparing WCET and Resource Demands of Trigonometric Functions Implemented as Iterative Calculations vs. Table-Lookup |
Kirner, Raimund et al. |
2006 |
