OASIcs.PARMA-DITAM.2023.3.pdf
- Filesize: 0.56 MB
- 12 pages
Document
RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper)
Authors
Francesco Barchi 
,
Giacomo Pasini ,
Emanuele Parisi ,
Giuseppe Tagliavini ,
Andrea Bartolini ,
Andrea Acquaviva
-
Part of:
Volume:
14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)
Series: Open Access Series in Informatics (OASIcs)
Conference: Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures (PARMA)
Conference: Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (DITAM) - License:
Creative Commons Attribution 4.0 International license
- Publication Date: 2023-03-13
File
Document Identifiers
Author Details
Cite AsGet BibTex
Francesco Barchi, Giacomo Pasini, Emanuele Parisi, Giuseppe Tagliavini, Andrea Bartolini, and Andrea Acquaviva. RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper). In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 3:1-3:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.3
https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.3
Abstract
Nowadays, the development of security applications is a relevant topic in the Internet of Things (IoT) and cyber-physical systems (CPS) fields. Different embedded architectures have been adopted in these areas, but the RISC-V parallel ultra-low-power (PULP) architecture stands out as a particularly efficient system. However, it has never been proposed to enable cryptography. In the context of video stream security, stream ciphers enable an efficient solution to ensure data privacy, and the exploitation of the PULP multi-core accelerator cluster paves the way to an efficient implementation of these ciphers. In this paper, we exploit the capability of the PULP architecture coupled with the code safety provided by the RUST programming language to design and implement an efficient stream encryption algorithm. We present a wrapper system between the development libraries of a PULP platform enabling the secure execution of a verified RUST-written implementation of ChaCha20 and AES-CTR, targeting a microdrones based video surveillance system. Experimental tests have resulted in an encryption efficiency of ChaCha20 of 2.3 cycles per Byte (cB), placing the resulting implementation at the state-of-the-art, in direct competition with higher-class architectures like Apple M1 (2.0 cB).
Subject Classification
ACM Subject Classification
- Hardware → Emerging languages and compilers
- Computer systems organization → Multicore architectures
- Computer systems organization → Embedded software
- Software and its engineering → Embedded software
Keywords
- Parallel Low-Power Embedded Systems
- Rust
- RISC-V
- Stream Cipher
Metrics
- Access Statistics
-
Total Accesses (updated on a weekly basis)
0PDF Downloads
References
- URL: https://cybelangel.com/hype-cycle-for-cyber-risk-management-2022/.
- URL: https://doc.rust-lang.org/nomicon/.
- URL: https://github.com/RustCrypto/stream-ciphers.
- URL: https://bench.cr.yp.to/results-stream.html.
- The Transport Layer Security (TLS) Protocol Version 1.3. URL: https://www.rfc-editor.org/rfc/rfc8446.
-
Alexandre Adomnicai and Thomas Peyrin. Fixslicing aes-like ciphers: New bitsliced aes speed records on arm-cortex m and risc-v. Cryptology ePrint Archive, 2020.
-
Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kağan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, et al. An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(9):2481-2494, 2017.
-
Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K Gürkaynak, and Luca Benini. Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017.
-
Wojciech Giernacki, Mateusz Skwierczyński, Wojciech Witwicki, Paweł Wroński, and Piotr Kozierski. Crazyflie 2.0 quadrotor as a platform for research and education in robotics and control engineering. In 2017 22nd International Conference on Methods and Models in Automation and Robotics (MMAR), pages 37-42. IEEE, 2017.
-
Ralf Jung, Jacques-Henri Jourdan, Robbert Krebbers, and Derek Dreyer. RustBelt: Securing the foundations of the Rust programming language. Proceedings of the ACM on Programming Languages, 2(POPL):1-34, 2017.
-
Nicholas D Matsakis and Felix S Klock. The rust language. ACM SIGAda Ada Letters, 34(3):103-104, 2014.
-
Mitsuru Matsui and Junko Nakajima. On the power of bitslice implementation on intel core2 processor. In International Workshop on Cryptographic Hardware and Embedded Systems, pages 121-134. Springer, 2007.
- Yoav Nir and Adam Langley. ChaCha20 and Poly1305 for IETF Protocols. Rfc 1654, RFC Editor, June 2018. URL: https://www.rfc-editor.org/rfc/rfc8439.
-
Daniele Palossi, Francesco Conti, and Luca Benini. An open source and open hardware deep learning-powered visual navigation engine for autonomous nano-UAVs. In 2019 15th International Conference on Distributed Computing in Sensor Systems (DCOSS), pages 604-611. IEEE, 2019.
-
D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, and L. Benini. PULP: A parallel ultra low power platform for next generation IoT applications. In 2015 IEEE Hot Chips 27 Symposium (HCS), 2015.
-
Andreas Traber, Florian Zaruba, Sven Stucki, Antonio Pullini, Germain Haugou, Eric Flamand, Frank K Gurkaynak, and Luca Benini. PULPino: A small single-core RISC-V SoC. In 3rd RISCV Workshop, 2016.