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IRQ Coloring: Mitigating Interrupt-Generated Interference on ARM Multicore Platforms

Authors Diogo Costa , Luca Cuomo, Daniel Oliveira , Ida Maria Savino, Bruno Morelli , José Martins , Fabrizio Tronci, Alessandro Biasci , Sandro Pinto

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Author Details

Diogo Costa
  • Centro ALGORITMI / LASI, University of Minho, Portugal
Luca Cuomo
  • Huawei Pisa Research Center, Pisa, Italy
Daniel Oliveira
  • Centro ALGORITMI / LASI, University of Minho, Portugal
Ida Maria Savino
  • Huawei Pisa Research Center, Pisa, Italy
Bruno Morelli
  • Huawei Pisa Research Center, Pisa, Italy
José Martins
  • Centro ALGORITMI / LASI, University of Minho, Portugal
Fabrizio Tronci
  • Huawei Pisa Research Center, Pisa, Italy
Alessandro Biasci
  • Huawei Pisa Research Center, Pisa, Italy
Sandro Pinto
  • Centro ALGORITMI / LASI, University of Minho, Portugal

Funding

  • Costa, Diogo: Supported by Centro Algoritmi grant IRQ-COL-HYP-HUAWEI_01.
  • Oliveira, Daniel: Supported by FCT grant 2020.04585.BD.
  • Martins, José: Supported by FCT grant SFRH/BD/138660/2018.

Cite AsGet BibTex

Diogo Costa, Luca Cuomo, Daniel Oliveira, Ida Maria Savino, Bruno Morelli, José Martins, Fabrizio Tronci, Alessandro Biasci, and Sandro Pinto. IRQ Coloring: Mitigating Interrupt-Generated Interference on ARM Multicore Platforms. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 2:1-2:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
https://doi.org/10.4230/OASIcs.NG-RES.2023.2

Abstract

Mixed-criticality systems, which consolidate workloads with different criticalities, must comply with stringent spatial and temporal isolation requirements imposed by safety-critical standards (e.g., ISO26262). This, per se, has proven to be a challenge with the advent of multicore platforms due to the inner interference created by multiple subsystems while disputing access to shared resources. With this work, we pioneer the concept of Interrupt (IRQ) coloring as a novel mechanism to minimize the interference created by co-existing interrupt-driven workloads. The main idea consists of selectively deactivating specific ("colored") interrupts if the QoS of critical workloads (e.g., Virtual Machines) drops below a well-defined threshold. The IRQ Coloring approach encompasses two artifacts, i.e., the IRQ Coloring Design-Time Tool (IRQ DTT) and the IRQ Coloring Run-Time Mechanism (IRQ RTM). In this paper, we focus on presenting the conceptual IRQ coloring design, describing the first prototype of the IRQ RTM on Bao hypervisor, and providing initial evidence about the effectiveness of the proposed approach on a synthetic use case.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time system specification
  • Computer systems organization → Embedded software
Keywords
  • IRQ coloring
  • Interrupt Interference
  • Mixed-Criticality Systems
  • Hypervisors
  • Bao
  • Arm

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References

  1. Jaume Abella, Carles Hernández, Eduardo Quiñones, Francisco J Cazorla, Philippa Ryan Conmy, Mikel Azkarate-Askasua, Jon Perez, Enrico Mezzetti, and Tullio Vardanega. Wcet analysis methods: Pitfalls and challenges on their trustworthiness. In 10th IEEE International Symposium on Industrial Embedded Systems (SIES), pages 1-10, 2015. Google Scholar
  2. Michael G Bechtel and Heechul Yun. Denial-of-service attacks on shared cache in multicore: Analysis and prevention, 2019. Google Scholar
  3. Francisco J Cazorla, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernandez, Jaume Abella, and Tullio Vardanega. Probabilistic worst-case timing analysis: Taxonomy and comprehensive survey. ACM Computing Surveys (CSUR), 52(1):1-35, 2019. Google Scholar
  4. Francisco J Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu, Benoit Triquet, Guillem Bernat, Emery Berger, Jaume Abella, Franck Wartel, Michael Houston, et al. Proartis: Probabilistically analyzable real-time systems. ACM Transactions on Embedded Computing Systems (TECS), 12(2s):1-26, 2013. Google Scholar
  5. Jon Perez Cerrolaza, Roman Obermaisser, Jaume Abella, Francisco J Cazorla, Kim Grüttner, Irune Agirre, Hamidreza Ahmadian, and Imanol Allende. Multi-core devices for safety-critical systems: A survey. ACM Computing Surveys (CSUR), 53(4):1-38, 2020. Google Scholar
  6. Alfons Crespo, Patricia Balbastre, José Simó, Javier Coronel, Daniel Gracia Pérez, and Philippe Bonnot. Hypervisor-based multicore feedback control of mixed-criticality systems. IEEE Access, 6:50627-50640, 2018. Google Scholar
  7. Dakshina Dasari, Benny Akesson, Vincent Nelis, Muhammad Ali Awan, and Stefan M Petters. Identifying the sources of unpredictability in cots-based multicore systems. In 8th IEEE international symposium on industrial embedded systems (SIES), pages 39-48, 2013. Google Scholar
  8. Farzad Farshchi, Qijing Huang, and Heechul Yun. Bru: Bandwidth regulation unit for real-time multicore processors. In 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 364-375, 2020. Google Scholar
  9. Gabriel Fernandez, Jaume Abella Ferrer, Eduardo Quiñones, Christine Rochange, Tullio Vardanega, and Francisco Javier Cazorla Almeida. Contention in multicore hardware shared resources: Understanding of the state of the art. In 14th International Workshop on Worst-Case Execution Time Analysis, pages 31-42, 2014. Google Scholar
  10. Robert Gifford, Neeraj Gandhi, Linh Thi Xuan Phan, and Andreas Haeberlen. Dna: Dynamic resource allocation for soft real-time multicore systems. In 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 196-209, 2021. Google Scholar
  11. Giovani Gracioli, Rohan Tabish, Renato Mancuso, Reza Mirosanlou, Rodolfo Pellizzoni, and Marco Caccamo. Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms. In 31st Euromicro Conference on Real-Time Systems (ECRTS), volume 133, pages 27:1-27:25, 2019. Google Scholar
  12. Mohamed Hassan, Anirudh M Kaushik, and Hiren Patel. Predictable cache coherence for multi-core real-time systems. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 235-246, 2017. Google Scholar
  13. Thomas A Henzinger and Joseph Sifakis. The embedded systems design challenge. In International Symposium on Formal Methods, pages 1-15, 2006. Google Scholar
  14. Joo-Young Hwang, Sang-Bum Suh, Sung-Kwan Heo, Chan-Ju Park, Jae-Min Ryu, Seong-Yeol Park, and Chul-Ryun Kim. Xen on arm: System virtualization using xen hypervisor for arm-based secure mobile phones. In 5th IEEE Consumer Communications and Networking Conference, pages 257-261, 2008. Google Scholar
  15. Hyoseung Kim and Ragunathan Rajkumar. Predictable shared cache management for multi-core real-time virtualization. ACM Transactions on Embedded Computing Systems (TECS), volume 17, 2017. Google Scholar
  16. Tomasz Kloda, Marco Solieri, Renato Mancuso, Nicola Capodieci, Paolo Valente, and Marko Bertogna. Deterministic memory hierarchy and virtualization for modern multi-core embedded systems. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 1-14, 2019. Google Scholar
  17. Ondrej Kotaba, Jan Nowotsch, Michael Paulitsch, Stefan M Petters, and Henrik Theiling. Multicore in real-time systems-temporal isolation challenges due to shared resources. In 16th Design, Automation & Test in Europe Conference and Exhibition, 2013. Google Scholar
  18. Andreas Löfwenmark and Simin Nadjm-Tehrani. Understanding shared memory bank access interference in multi-core avionics. In 16th International Workshop on Worst-Case Execution Time Analysis, 2016. Google Scholar
  19. Renato Mancuso, Roman Dudko, Emiliano Betti, Marco Cesati, Marco Caccamo, and Rodolfo Pellizzoni. Real-time cache management framework for multi-core architectures. In IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 45-54, 2013. Google Scholar
  20. José Martins, Adriano Tavares, Marco Solieri, Marko Bertogna, and Sandro Pinto. Bao: A Lightweight Static Partitioning Hypervisor for Modern Multi-Core Embedded Systems. In Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2020), volume 77, pages 3:1-3:14, 2020. Google Scholar
  21. Paolo Modica, Alessandro Biondi, Giorgio Buttazzo, and Anup Patel. Supporting temporal and spatial isolation in a hypervisor for arm multicore platforms. In IEEE International Conference on Industrial Technology (ICIT), pages 1651-1657, 2018. Google Scholar
  22. Sandro Pinto, Hugo Araujo, Daniel Oliveira, Jose Martins, and Adriano Tavares. Virtualization on trustzone-enabled microcontrollers? voilà! In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 293-304. IEEE, 2019. Google Scholar
  23. Sandro Pinto, Jorge Pereira, Tiago Gomes, Adriano Tavares, and Jorge Cabral. Ltzvisor: Trustzone is the key. In 29th Euromicro Conference on Real-Time Systems (ECRTS), 2017. Google Scholar
  24. Ralf Ramsauer, Jan Kiszka, Daniel Lohmann, and Wolfgang Mauerer. Look mum, no vm exits! (almost). arXiv preprint, 2017. URL: http://arxiv.org/abs/1705.06932.
  25. Daniel J Sorin, Mark D Hill, and David A Wood. A primer on memory consistency and cache coherence. In Synthesis lectures on computer architecture, volume 6, pages 1-212, 2011. Google Scholar
  26. Theo Ungerer, Francisco Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quinones, Mike Gerdes, Marco Paolieri, Julian Wolf, et al. Merasa: Multicore execution of hard real-time applications supporting analyzability. IEEE Micro, 30(5):66-75, 2010. Google Scholar
  27. Heechul Yun, Renato Mancuso, Zheng-Pei Wu, and Rodolfo Pellizzoni. PALLOC: Dram bank-aware memory allocator for performance isolation on multicore platforms. In IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 155-166, 2014. Google Scholar
  28. Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, and Lui Sha. Memory access control in multiprocessor for real-time systems with mixed criticality. In 24th Euromicro Conference on Real-Time Systems, pages 299-308, 2012. Google Scholar
  29. Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, and Lui Sha. Memguard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 55-64, 2013. Google Scholar
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