Best Practice for Caching of Single-Path Code

Authors Martin Schoeberl, Bekim Cilku, Daniel Prokesch, Peter Puschner



PDF
Thumbnail PDF

File

OASIcs.WCET.2017.2.pdf
  • Filesize: 0.49 MB
  • 12 pages

Document Identifiers

Author Details

Martin Schoeberl
Bekim Cilku
Daniel Prokesch
Peter Puschner

Cite AsGet BibTex

Martin Schoeberl, Bekim Cilku, Daniel Prokesch, and Peter Puschner. Best Practice for Caching of Single-Path Code. In 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017). Open Access Series in Informatics (OASIcs), Volume 57, pp. 2:1-2:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
https://doi.org/10.4230/OASIcs.WCET.2017.2

Abstract

Single-path code has some unique properties that make it interesting to explore different caching and prefetching alternatives for the stream of instructions. In this paper, we explore different cache organizations and how they perform with single-path code.
Keywords
  • single-path code
  • method cache
  • prefetching

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. J. Allen, K. Kennedy, C. Porterfield, and J. Warren. Conversion of Control Dependence to Data Dependence. In Proc. 10th ACM Symposium on Principles of Programming Languages, pages 177-189, Jan. 1983. Google Scholar
  2. Bekim Cilku, Daniel Prokesch, and Peter Puschner. A time-predictable instruction-cache architecture that uses prefetching and cache locking. In Proc. 18th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC) Workshops, 11th IEEE/IFIP International Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS), pages 74-79. IEEE CS Press, 2015. Google Scholar
  3. Bekim Cilku, Wolfgang Puffitsch, Daniel Prokesch, Martin Schoeberl, and Peter Puschner. Improving performance of single-path code through a time-predictable memory hierarchy. In Proceedings of the 20th IEEE International Symposium on Real-Time Computing (ISORC 2017), Toronto, Canada, May 2017. IEEE. Google Scholar
  4. Philipp Degasperi, Stefan Hepp, Wolfgang Puffitsch, and Martin Schoeberl. A Method Cache for Patmos. In Proceedings of the 17th IEEE Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC 2014), pages 100-108, Reno, Nevada, USA, June 2014. IEEE. URL: http://dx.doi.org/10.1109/ISORC.2014.47.
  5. Huping Ding, Yun Liang, and Tulika Mitra. Wcet-centric dynamic instruction cache locking. In Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, pages 1-6. IEEE, 2014. Google Scholar
  6. Heiko Falk, Sebastian Altmeyer, Peter Hellinckx, Björn Lisper, Wolfgang Puffitsch, Christine Rochange, Martin Schoeberl, Rasmus Bo Sørensen, Peter Wägemann, and Simon Wegener. TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research. In Martin Schoeberl, editor, 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), volume 55 of OpenAccess Series in Informatics (OASIcs), pages 2:1-2:10. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016. URL: http://dx.doi.org/10.4230/OASIcs.WCET.2016.2.
  7. Heiko Falk, Sascha Plazar, and Henrik Theiling. Compile-time decided instruction cache locking using worst-case execution paths. In Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pages 143-148. ACM, 2007. Google Scholar
  8. Reinhold Heckmann and Christian Ferdinand. Worst-Case Execution Time Prediction by Static Program Analysis. [Online, last accessed November 2013]. URL: http://www.absint.de/aiT_WCET.pdf.
  9. Reinhold Heckmann, Marc Langenbach, Stephan Thesing, and Reinhard Wilhelm. The influence of processor architecture on the design and the results of wcet tools. Proceedings of the IEEE, 91(7):1038-1054, 2003. Google Scholar
  10. Stefan Hepp and Florian Brandner. Splitting functions into single-entry regions. In Karam S. Chatha, Rolf Ernst, Anand Raghunathan, and Ravishankar Iyer, editors, 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2014, Uttar Pradesh, India, October 12-17, 2014, pages 17:1-17:10. ACM, 2014. URL: http://dx.doi.org/10.1145/2656106.2656128.
  11. Stefan Hepp, Benedikt Huber, Jens Knoop, Daniel Prokesch, and Peter P. Puschner. The platin tool kit - the T-CREST approach for compiler and WCET integration. In Proceedings 18th Kolloquium Programmiersprachen und Grundlagen der Programmierung, KPS 2015, Pörtschach, Austria, October 5-7, 2015, 2015. Google Scholar
  12. Mingsong Lv, Nan Guan, Jan Reineke, Reinhard Wilhelm, and Wang Yi. A survey on static cache analysis for real-time systems. Leibniz Transactions on Embedded Systems, 3(1):05-1, 2016. Google Scholar
  13. Daniel Prokesch, Benedikt Huber, and Peter P. Puschner. Towards automated generation of time-predictable code. In Heiko Falk, editor, 14th International Workshop on Worst-Case Execution Time Analysis, WCET 2014, July 8, 2014, Ulm, Germany, volume 39 of OASICS, pages 103-112. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, 2014. Google Scholar
  14. Isabelle Puaut and David Decotigny. Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In Real-Time Systems Symposium, 2002. RTSS 2002. 23rd IEEE, pages 114-123. IEEE, 2002. Google Scholar
  15. Peter Puschner and Alan Burns. Writing temporally predictable code. In Proceedings of the The Seventh IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS 2002), pages 85-94, Washington, DC, USA, 2002. IEEE Computer Society. URL: http://dx.doi.org/10.1109/WORDS.2002.1000040.
  16. Peter Puschner, Daniel Prokesch, Benedikt Huber, Jens Knoop, Stefan Hepp, and Gernot Gebhard. The T-CREST approach of compiler and WCET-analysis integration. In 9th Workshop on Software Technologies for Future Embedded and Ubiquitious Systems (SEUS 2013), pages 33-40, 2013. Google Scholar
  17. Jan Reineke, Daniel Grund, Christoph Berg, and Reinhard Wilhelm. Timing predictability of cache replacement policies. Real-Time Systems, 37(2):99-122, 2007. Google Scholar
  18. Martin Schoeberl. A time predictable instruction cache for a Java processor. In On the Move to Meaningful Internet Systems 2004: Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES 2004), volume 3292 of LNCS, pages 371-382, Agia Napa, Cyprus, October 2004. Springer. URL: http://dx.doi.org/10.1007/b102133.
  19. Martin Schoeberl, Sahar Abbaspour, Benny Akesson, Neil Audsley, Raffaele Capasso, Jamie Garside, Kees Goossens, Sven Goossens, Scott Hansen, Reinhold Heckmann, Stefan Hepp, Benedikt Huber, Alexander Jordan, Evangelia Kasapaki, Jens Knoop, Yonghui Li, Daniel Prokesch, Wolfgang Puffitsch, Peter Puschner, André Rocha, Cláudio Silva, Jens Sparsø, and Alessandro Tocchi. T-CREST: Time-predictable multi-core architecture for embedded systems. Journal of Systems Architecture, 61(9):449-471, 2015. URL: http://dx.doi.org/10.1016/j.sysarc.2015.04.002.
  20. Martin Schoeberl, Florian Brandner, Stefan Hepp, Wolfgang Puffitsch, and Daniel Prokesch. Patmos reference handbook. Technical report, Technical University of Denmark, 2014. Google Scholar
  21. Martin Schoeberl, Pascal Schleuniger, Wolfgang Puffitsch, Florian Brandner, Christian W. Probst, Sven Karlsson, and Tommy Thorn. Towards a time-predictable dual-issue microprocessor: The Patmos approach. In First Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems (PPES 2011), pages 11-20, Grenoble, France, March 2011. Google Scholar
  22. Jack Whitham and Martin Schoeberl. WCET-based comparison of an instruction scratchpad and a method cache. In Proceedings of the 10th Workshop on Software Technologies for Embedded and Ubiquitous Systems (SEUS 2014), Reno, Nevada, USA, June 2014. URL: http://dx.doi.org/10.1109/ISORC.2014.48.
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail