Bounded Depth Circuits with Weighted Symmetric Gates : Satisfiability , Lower Bounds and Compression ∗

A Boolean functionf : {0,1}n→{0,1} is weighted symmetric if there exist a functiong :Z→{0,1} and integersw0,w1, . . . ,wn such thatf (x1, . . . ,xn) = g(w0+∑i=1wixi) holds. In this paper, we present algorithms for the circuit satisfiability problem of bounded depth circuits with AND, OR, NOT gates and a limited number of weighted symmetric gates. Our algorithms run in time super-polynomially faster than 2 n even when the number of gates is super-polynomial and the maximum weight of symmetric gates is nearly exponential. With an additional trick, we give an algorithm for the maximum satisfiability problem that runs in time poly (nt) ·2n−n for instances withn variables,O(nt) clauses andarbitrary weights. To the best of our knowledge, this is the first moderately exponential time algorithm even for Max 2SAT instances with arbitrary weights. Through the analysis of our algorithms, we obtain average-case lower bounds and compression algorithms for such circuits and worst-case lower bounds for majority votes of such circuits, where all the lower bounds are against the generalized Andreev function. Our average-case lower bounds might be of independent interest in the sense that previous ones for similar circuits with arbitrary symmetric gates rely on communication complexity lower bounds while ours are based on the restriction method.


Introduction
We are concerned with bounded depth circuits with AND, OR, NOT and (weighted) symmetric gates.Let Z be the set of integers and x 1 , x 2 . . . ., x n be Boolean variables.A Boolean function f : {0, 1} n → {0, 1} is weighted symmetric if there exist a function g : Z → {0, 1} and integers w 0 , w 1 , . . ., w n such that f (x 1 , . . ., x n ) = g(w 0 + n i=1 w i x i ) holds.If w 1 = w 2 = • • • = w n = 1 holds, then f is symmetric.
For example, if we set g(z) = sgn(z), where sgn(z) = 1 if and only if z ≥ 0, we obtain majority functions as symmetric functions and linear threshold functions as weighted symmetric functions.If we define g(z) = 1 if and only if z ≡ 0 mod m for an integer m ≥ 2, then we obtain modulo m functions as symmetric functions.
A (weighted) symmetric gate is a logic gate that computes a (weighted) symmetric function.We denote by SYM w the set of weighted symmetric gates such that max i |w i | ≤ w holds.When we consider satisfiability and compression algorithms, we assume that g(z) can be evaluated in time polynomial in log 2 |z|, where |z| denotes the absolute value of z.When we consider circuit lower bounds, we assume that g is computable, i.e., there exists a Turing machine that computes g.

Our contribution
Satisfiability Algorithms: In the circuit satisfiability problem (Circuit SAT), our task is, given a Boolean circuit C, to decide whether there exists a 0/1 assignment to the input variables such that C evaluates 1.If input instances are restricted to a class of Boolean circuits C, the problem is called C-SAT.A naïve algorithm can solve Circuit SAT in time O(poly(|C|)•2 n ), where we denote by |C| the size of C and by n the number of input variables of C respectively.We say an algorithm for C-SAT is moderately exponential time if it checks the satisfiability of every C ∈ C in time poly(|C|) • 2 n−ω(log n) , i.e., super-polynomially faster than 2 n .We are interested in for which class C moderately exponential time satisfiability algorithms exist.
Let SYM w •AND(n, m) be the set of n-variate depth 2 circuits with a weighted symmetric gate in SYM w at the top and at most m AND gates at the bottom.Let SYM w • AC 0 d (n, m) be the set of n-variate unbounded fan-in depth d + 1 layered circuits with AND, OR, NOT gates and a weighted symmetric gate in SYM w such that the top gate is the weighted symmetric gate and each layer contains at most m gates.Let AC 0 d [SYM w ](n, m, t) be the set of n-variate unbounded fan-in depth d layered circuits with AND, OR, NOT gates and at most t weighted symmetric gates in SYM w such that each layer contains at most m gates.
In this paper, we show moderately exponential time algorithms for the counting version of C-SAT, where Theorem 1 (depth 2, weighted symmetric gate at the top, AND gates at the bottom).We can count the number of satisfying assignments for C ∈ SYM w • AND(n, m) deterministically in time poly(n, m, log w) • 2 n−Ω((n/ log(mw)) log n/4 log(nm) ) and exponential space.
The running time is super-polynomially faster than 2 n when, e.g., m = n o(log n/ log log n) and w = 2 n 0.99 .Note that SYM 2 n contains all Boolean functions (if we ignore the assumption that g(z) can be evaluated in time polynomial in log 2 |z|).The heart of our algorithms is a (seemingly new) bottom fan-in reduction technique inspired by recent developments on the analysis of "greedy restriction" by "concentrated shrinkage" [51,54,17,49].With an additional trick, we give an algorithm for the maximum satisfiability problem that runs in time poly(n t ) • 2 n−n 1/O(t) for instances with n variables, O(n t ) clauses and arbitrary weights.To the best of our knowledge, this is the first moderately exponential time algorithm even for Max 2SAT instances with arbitrary weights.
We extend the above algorithm with the help of the depth reduction algorithm due to Beame, Impagliazzo and Srinivasan [7].
Theorem 2 (depth d, weighted symmetric gate only at the top).We can count the number of satisfying assignments for and exponential space.
The running time is super-polynomially faster than 2 n when, e.g., m = 2 (log n/4d)  , where c ≤ log 1/4 n 2(4d) 5/4 .Although our algorithms run in time super-polynomially faster than 2 n instead of exponentially faster than 2 n (2 (1−ε)n for a universal constant ε > 0), this seems unavoidable due to the Strong Exponential Time Hypothesis (SETH) [12,32,34]: The hypothesis states that for all k, there exists ε k > 0 such that the satisfiability problem of k-CNF formulas cannot be solved in time 2 (1−ε k )n .SETH has been used in proving conditional time lower bounds for several exponential time and polynomial time algorithms, see, e.g., [21,37,40].
Circuit Lower Bounds: Through the analysis of our satisfiability algorithms, we obtain the following average-case lower bounds.
Theorem 4 (depth 2, weighted symmetric gate at the top, AND gates at the bottom).There exists a constant α > 0 such that for every m, w and sufficiently large n, there exists a polynomial time computable function f n,m,w such that for every C ∈ SYM w • AND(n, m), it holds that + 2 −Ω((n/ log(mw)) α log n/ log(nm) ) .
We also obtain similar average-case lower bounds for SYM w • AC 0 d (n, m) and AC 0 d [SYM w ](n, m, t), see Theorems 12 and 13 in Section 5. Our average-case lower bounds might be interesting in the sense that (1) previous ones for similar circuits with arbitrary symmetric gates rely on communication complexity lower M F C S 2 0 1 6 82:4 Bounded Depth Circuits with Weighted Symmetric Gates bounds while ours are based on the restriction method and (2) we are not aware of (even worst-case) lower bounds for SYM w • AND with w = n ω(log n) .
Let C be a set of Boolean circuits and MAJ • C be the set of Boolean circuits, where C ∈ MAJ • C is a majority vote of C circuits, i.e., C(x) = sgn(C 1 (x) + • • • + C s (x) + w 0 ) holds for some C 1 , . . ., C s ∈ C and an integer w 0 .
Combining the above average-case lower bounds and the discriminator lemma due to Hajnal, Maass, Pudlák, Szegedy and Turán [27], we obtain the following worst-case lower bounds.
Theorem 5 (majority vote of depth 2, weighted symmetric gate at the top, AND gates at the bottom).There exists a constant α > 0 such that for every m, w and sufficiently large n, there exists a polynomial time computable function f n,m,w such that any C ∈ MAJ • SYM w • AND(n, m) cannot compute f n,m,w if the majority gate at the top of C has fan-in at most 2 o((n/ log(mw)) α log n/ log(nm) ) .
We also obtain similar worst-case lower bounds for MAJ Compression Algorithms: In the circuit compression problem (Circuit CMP), our task is, given the truth table of an s-sized Boolean circuit C and an integer s ≥ s, to construct a Boolean circuit C that is at most s -sized and computes the same function as C. If input instances are restricted to a class of Boolean circuits C, the problem is called C-CMP.In C-CMP, we do not have to construct C as a circuit in C. Since every n-variate Boolean function can be represented as a (1+o(1))2 n n -sized circuit [39] 1 , the problem is interesting if s 2 n /n and in particular we consider the case s = 2 n−ω(log n) .A compression algorithm is efficient if it runs in time 2 O(n) given the truth table of an n-variate Boolean function.Note that input length is 2 n and an efficient algorithm runs in polynomial time.The running time analyses of our satisfiability algorithms imply efficient compression algorithms.Let C ∈ {SYM w •AND(n, m), We obtain deterministic efficient algorithms for C-CMP if parameters n, m, w, d, t are such that the corresponding algorithms for C-SAT run in time 2 n−ω(log n) .

Background
Bounded Depth Circuits with (Weighted) Symmetric Gates: Let AC 0 be the set of bounded depth circuits with AND, OR and NOT gates, AC 0 [m] be the set of AC 0 circuits with modulo m gates, AC 0 [MAJ] be the set of AC 0 circuits with majority gates (also known as TC 0 ), AC 0 [THR] be the set of AC 0 circuits with linear threshold gates and AC 0 [SYM w ] be the set of AC 0 circuits with gates in SYM w .Note that for every linear threshold gate, there exists a polynomial size depth 2 majority circuit that computes it [24].
In their seminal work, Razborov [46] and Smolensky [55] showed exponential lower bounds on the size of AC 0 [m] circuits computing majority or mod q functions when m, q are prime powers and relatively prime.Since then, people have been trying to obtain super-polynomial size lower bounds against stronger circuit classes such as AC 0 [m] with arbitrary m or AC 0 [MAJ].Despite much effort of researchers, super-polynomial size lower bounds have been only shown for such circuit classes with some restriction, see, e.g., [4,9,14,22,23,26,27,28] (here we consider circuits computing "explicit" Boolean functions, i.e., functions in NP).
One of the best studied restriction is limiting the number of (weighted) symmetric gates.The following lower bounds are known: (Worst-case lower bounds) Exponential lower bounds for AC 0 [MAJ] circuits with n o(1) majority gates [6, 8] and AC 0 [THR] circuits with o(log n) linear threshold gates [44].
(Average-case lower bounds) super-polynomial lower bounds for AC 0 [SYM 1 ] circuits with o(log 2 n) symmetric gates [58]; arbitrary large polynomial lower bounds for AC 0 [SYM 1 ] circuits with n 1−o(1) symmetric gates and AC 0 [THR] circuits with n 1/2−o(1) linear threshold gates [38].The above average-case lower bounds are based on the results of Håstad and Goldmann [29] and Razborov and Wigderson [48] that show average-case lower bounds for SYM 1 • AND circuits from the communication complexity lower bounds due to Babai, Nisan and Szegedy [5] and also show worst-case lower bounds for MAJ • SYM 1 • AND circuits using the discriminator lemma.
Circuit Satisfiability: Studying moderately exponential time algorithms for Circuit SAT is motivated by not only the importance in practice, e.g., logic circuit design and constraint satisfaction but also the viewpoint of Boolean circuit complexity.As pointed out by several papers such as [60,65], there are strong connections between proving circuit lower bounds for C and designing moderately exponential time algorithms for C-SAT; see also excellent surveys [52,43,62].Typical such connections are: (1) Some proof techniques such as deterministic/random restriction (shrinkage analysis/switching lemma) simultaneously prove circuit lower bounds for C and provides C-SAT algorithms [51,31,7,54,17,16,15,20,25].
(2) Williams [60,64] showed that if we obtain a moderately exponential time algorithm for C-SAT and C satisfies some closure property, then we also have a separation of complexity classes such as E NP C or NE C, where E NP is the set of languages decidable by exponential time Turing machines with NP oracles and NE is the set of languages decidable by non-deterministic exponential time Turing machines; see also [59,61,63,10,35] for the improvement of such connections.Since then, people have developed moderately exponential time satisfiability algorithms for various circuit classes [33,18,30,1,3,2,42,19,57]. In particular, one of the current best lower bounds, NE ACC 0 • THR (also NE ACC 0 • SYM 1 ), was obtained through satisfiability algorithms [63], where Circuit Compression: Circuit CMP is a relaxed version of the circuit minimization problem.Chen, Kabanets, Kolokolova, Shaltiel and Zuckerman [17] established a connection between compression algorithms and circuit lower bounds as follows: If there exists a deterministic efficient algorithm for C-CMP, then NEXP C. They also gave efficient compression algorithms for AC 0 circuits, Boolean formulas and branching programs of certain size range.Srinivasan [56] showed an efficient compression algorithm for AC 0 [m] with a prime power m.Carmosino, Impagliazzo, Kabanets and Kolokolova [13] established interesting connections between the tasks of compression/learning and "natural properties" in the sense of Razborov and Rudich [47].

Preliminaries
We use random access machines as our computation model.For a set S, we denote by |S| the cardinality of S.

Bounded Depth Circuits with Weighted Symmetric Gates
A literal is either a Boolean variable or its negation.A term is a conjunction of literals.A Boolean circuit is a directed acyclic graph whose source nodes are labeled by literals or constants and internal and sink nodes are labeled by logic gates such as AND, OR, NOT, or weighted symmetric gates.A Boolean circuit with a single sink node computes a Boolean function in a natural way.We call source nodes and a sink node input nodes and output node respectively.The depth of a node is defined as the length of the longest path from it to the output node.The depth of a Boolean circuit is the maximum value of the depth over all nodes.A Boolean circuit is layered if for every edge (u, v), u and v have depth d and d + 1 for some d.
A Boolean circuit C : {0, 1} n → {0, 1} is satisfiable if there exists a satisfying assignment for C, i.e., an assignment a ∈ {0, 1} n such that C(a) = 1 holds.For two Boolean functions (or circuits) f, g in the same variables, we write f ≡ g if f (a) = g(a) holds for all a ∈ {0, 1} n .A Boolean function f : {0, 1} n → {0, 1} is k-junta if it depends on at most k variables, i.e., there exist g : {0, 1} k → {0, 1} and 1 The meaning of ρ is that if ρ(x i ) ∈ {0, 1}, then we assign the value ρ(x i ) to x i , and if ρ(x i ) = * , then we leave x i as it is.Thus, when we apply a restriction ρ to a Boolean function f , we obtain the Boolean function f | ρ defined over the variables ρ −1 ( * ).We also apply a restriction ρ to a Boolean circuit C and obtain a Boolean circuit C| ρ .When we apply a restriction ρ to a Boolean circuit C, we simplify a Boolean circuit C using the identities 0 ∧ f ≡ 0, 1 ∧ f ≡ f repeatedly (each appearance of L.H.S. is replaced by R.H.S.).
A restriction decision tree T over x 1 , . . ., x n is an ordinary decision tree except that leaves are not necessarily labeled by 0 or 1.The height of T is defined as the number of nodes on the longest path from the root to a leaf and the size of T is defined as the number of nodes in T .We identify a path from the root to a leaf with a restriction.A random root-to-leaf path is sampled by repeatedly selecting a child of the current node uniformly at random from the root.Note that a path of length is chosen with probability 2 − .

A Dynamic Programming Algorithm for SYM w • AND k
We denote by g • AND k (n, m, w) the set of n-variate Boolean circuits of the form g(w 0 + s i=1 w i t i ), where g : Z → {0, 1}, s ≤ m, w 0 , w 1 , . . ., w s ∈ Z, max 0≤i≤s |w i | ≤ w, and t 1 , . . ., t s are terms that contain at most k-literals such that t i = t j holds for i = j.We define We specify an element C in SYM w • AND k (n, m) as C = {g, w 0 , (t 1 , w 1 ), . . ., (t s , w s )} and call s and max 0≤i≤s |w i | the size and the maximum weight of C respectively.
For a restriction ρ, we simplify C| ρ = {g, w 0 , (t 1 | ρ , w 1 ), . . ., (t s | ρ , w s )} repeatedly if there exists a pair (i, j), 1 ≤ i < j ≤ s such that t i | ρ ≡ t j | ρ holds.That is, we delete (t j | ρ , w j ) and replace (t i | ρ , w i ) by (t i | ρ , w i + w j ).If there are multiple such pairs, we may handle them in arbitrary order.
Our first satisfiability algorithm for SYM w • AND k (n, m) is described in Fig. 1.The algorithm involves two parameters n , m that are specified in the proof of Theorem 6.
The basic idea is as follows: Step 1: We construct a  for C and n , m , w are appropriately chosen parameters.Furthermore, pairs are sorted in the lexicographical order with respect to the first coordinate C so that we can use binary search.To do so, we check the number of satisfying assignments for every circuit in g • AND k (n , m , w ) one by one in the lexicographical order using brute force search.
Step 2: Let C be an input instance in g • AND k (n, m, w).For each restriction ρ that assigns * to the first n variables of C, we check the number of satisfying assignments for C| ρ using binary search in T and output the sum of them.
We will show the following theorem.
Theorem 6.We can count the number of satisfying assignments for C ∈ SYM w • AND k (n, m) deterministically in time poly(n, m, log w) • 2 n−Ω((n/ log(mw)) 1/k ) ) and exponential space.
Proof.We denote by |g • AND k (n, m, w)| the cardinality of g • AND k (n, m, w).To evaluate the running time of (Step 1), we upper bound the size of the table T using the following fact.
Fact 7.For all m, we have Proof.Note that k i=0 2 i n i is the number of different terms that consist of at most k-literals (including a constant function 1).Each term has a weight in {−w, −w+1, . . ., w−1, w}.Thus, we have the first inequality.The second inequality follows from an elementary calculation.Thus, we can bound the running time of Lines 03-04 from above by 2 (k+1)(2n ) k log(2(m+1)w+1) × poly(m , log(mw)) • 2 n , where we set m = k i=0 2 i n i ≤ (k + 1)(2n ) k .Next we evaluate the running time of (Step 2).Note that the following guarantees that every C| ρ in Line 06 belongs to g • AND k (n , m , (m + 1) • w).= Θ((n/ log(mw)) 1/k ), the total running time of Algorithm1 is bounded from above by poly(n, m, log w) • 2 n−Ω((n/ log(mw)) 1/k ) .This completes the proof.
Remark.In the case when g(z) = sgn(z), we can reduce the weight of the top gate of C| ρ from (m + 1)w to 2 n O(k) efficiently by Theorem 16 in [41].With this trick, we can handle Max SAT instances with arbitrary weights.

A Greedy Restriction Algorithm for SYM w • AND k
For a term t, we denote by |t| the width of t, i.e., the number of literals in t and by var(t) the set of variables that appear in t (possibly negated).Let C ∈ SYM w • AND k (n, m) be a circuit {g, w 0 , (t 1 , w 1 ), . . ., (t s , w s )}.We define var (C) : Our second satisfiability algorithm for SYM w • AND k (n, m) is described in Fig. 2. The basic idea is as follows: Step 1: Choose a positive integer according to the input.We seek for a variable, say x, that occurs most frequently in terms of width at least .We recursively run the algorithm for C| x=0 and C| x=1 .Here C| x=a denotes the circuit obtained from C by applying a restriction ρ such that ρ(x) = a ∈ {0, 1} and ρ(x ) = * for x = x.
Step 2: If there is no term of width at least , we call Algorithm1.
We will show the following theorem which implies Theorem 1 by setting k = n.
Theorem 9. We can count the number of satisfying assignments for C ∈ SYM w • AND k (n, m) deterministically in time poly(n, m, log w) • 2 n−Ω((n/ log(mw)) log n/4 log(km) ) and exponential space.
Proof.Let us define a sequence of random variables {C i } inductively as C 0 := C and C i+1 := C i | x=a , where x = arg max x∈var(Ci) freq (C i , x) and a is a uniform random bit.
We can think of the computation of Algorithm2 as a rooted binary tree.That is, the root node is labeled with C 0 , the left and right children of the root are labeled with C 0 | x=0 and C 0 | x=1 , and so on.Then, if we pick a node of depth n − n uniformly at random, the distribution of its label is identical to that of the random variable C n−n .
• n in the above lemma, we have that is, we have L (C n−n ) < n /2 with probability at least 1 − 2 −n .If we set = 4 log(km) log n , then the total running time of Algorithm2 is bounded from above by the sum of poly(n, m, log w) according to whether L (C n−n ) ≥ n /2 holds or not.An elementary calculation completes the proof.
Remark.The novelty of our algorithm and its analysis is a new way of reducing the bottom fan-in of circuits in a greedy manner.Intuitively, given a SYM w • AND k circuit with m gates, greedy restriction produces a collection of SYM w • AND k circuits with k = O(log(km)/ log n) such that at least one of the circuits in the collection is satisfiable if and only if so is the original circuit.Note that previous techniques such as Schuler's width reduction [53,11] or the standard random restriction achieve k = O(log(m/n)) and this bound is not sufficient for our purpose.

Average-Case Circuit Lower Bounds
Through the analysis of our satisfiability algorithms, we obtain the following average-case lower bounds.
Theorem 11 (depth 2, weighted symmetric gate at the top, AND gates at the bottom).There exists a constant α > 0 such that for every m, w and sufficiently large n, there exists a polynomial time computable function f n,m,w such that for every C ∈ SYM w • AND(n, m), it holds that + 2 −Ω((n/ log(mw)) α log n/ log(nm) ) .
Theorem 12 (depth d, weighted symmetric gate only at the top).There exists a constant α > 0 such that for every m, w, d and sufficiently large n, there exists a polynomial time computable function f n,m,w,d such that for every −Ω (n/2 2d(log m) 4/5 log(mw)) α log n/ log m .
Theorem 13 (depth d, t(n) weighted symmetric gates).There exists a constant α > 0 such that for every m, w and sufficiently large n, there exists a polynomial time computable function f n,m,w,d,t such that for every , where m = m2 t+1 and w = (mw) 2 t+1 .
In the rest of this section, we give a proof of Theorem 11.The proof of Theorem 12 is similar and we omit proof.Theorem 13 immediately follows from Theorem 12 with the idea of the proof of Theorem 5.1 in [8].

Generalized Andreev function
In this section, we review the construction of average-case hard Boolean functions due to [17,36].We begin with some definitions.
We need the following explicit construction due to Rao.

Definition 18 (List-Decodable Code). A function
We are ready to define the average-case hard Boolean functions: The generalized Andreev function A n,k : {0, 1} 4n × {0, 1} n → {0, 1} is defined as A n,k (x, y) := (Enc n,0.9k (x)) Ext n,k (y) .Let K(x) denote the Kolmogorov complexity of a string x ∈ {0, 1} * .The following lemma plays an important role in the proofs of our average-case lower bounds.

Lemma 22.
For every C ∈ SYM w • AND(n, m), it holds that where γ > 0 is a universal constant from Lemma 20.
Assuming this, the proof of Theorem 11 is complete since by Fact 21, we have .

Proof of Lemma 22.
We can see that from the proofs of Theorems 6 and 9, C can be computed by a restriction decision tree T of height n − n such that (1) each leaf is labeled by a circuit in SYM w • AND k (n , m ) for some m , k , w and (2) except for a 2 −n Ω(1) fraction of leaves, such a circuit can be described by using at most n bits (due to Fact 7).Let σ(C) M F C S 2 0 1 6

82:12
Bounded Depth Circuits with Weighted Symmetric Gates denote the description length of a circuit C in a fixed encoding scheme.Let ρ be a random restriction sampled by selecting a leaf of T uniformly at random and y ρ be a uniform random element of {0, 1} ρ −1 ( * ) .Then, we have where the last inequality is by Item (2) above and Lemma 20.This completes the proof.

Worst-Case Lower Bounds
From the average-case lower bounds in Section 5, we obtain the following worst-case lower bounds.
Theorem 23 (majority vote of depth 2, weighted symmetric gate at the top, AND gates at the bottom).There exists a constant α > 0 such that for every m, w and sufficiently large n, there exists a polynomial time computable function f n,m,w such that C ∈ MAJ • SYM w • AND(n, m) cannot compute f n,m,w if the majority gate at the top of C has fan-in at most 2 o((n/ log(mw)) α log n/ log(nm) ) .We need a corollary of the discriminator lemma.
The running time is super-polynomially faster than 2 n when, e.g., m = n c , w = 2 n

Figure 1 A
Figure 1 A Dynamic Programming Algorithm for SYMw • AND k .

Figure 2 A
Figure 2 A Greedy Restriction Algorithm for SYMw • AND k .
where ∆(a, b) denotes the Hamming distance between a and b.

Theorem 24 (
majority vote of depth d, weighted symmetric gate only at the top).There exists a constant α > 0 such that for every m, w, d and sufficiently large n, there exists a polynomial time computable function f n,m,w,d such that any C ∈ MAJ • SYM w • AC 0 d (n, m) cannot compute f n,m,w,d if the majority gate at the top of C has fan-in at most 2 o (n/2 2d(log m) 4/5 log(mw)) α log n/ log m .Theorem 25 (majority vote of depth d, t(n) weighted symmetric gates).There exists a constant α > 0 such that for every m, w, d, t and sufficiently large n, there exists a polynomial time computable function f n,m,w,d,t such that any C ∈ MAJ • AC 0 d [SYM w ](n, m, t) cannot compute f n,m,w,d,t if the majority gate at the top of C has fan-in at most 2 o (n/2 2d(log m ) 4/5 log(m w )) α log n/ log m , where m = m2 t+1 and w = (mw) 2 t+1 .Theorem 26 (depth d, t(n) weighted symmetric gates).There exists a constant α > 0 such that for every m, w, d, t and sufficiently large n, there exists a polynomial time computable function f n,m,w,d,t such that any C ∈ AC 0 d [SYM w ](n, m, t) cannot compute f n,m,w,d,t if t = o (n/2 2d(log m ) 4/5 log(m w )) α log n/ log m holds, where m = m(t + 1) and w = m t w t+1 .