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Documents authored by Berekovic, Mladen

Document
DOI: 10.4230/OASIcs.NG-RES.2021.3
Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout

Authors: Philipp Jungklass and Mladen Berekovic

Published in: OASIcs, Volume 87, Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)

Abstract
Modern microcontrollers for safety-critical real-time systems use a hierarchical memory system to increase execution speed and memory capacity. For this purpose, flash memories, which offer high capacity at low transfer rates, are combined with scratchpad memories, which provide high access speed at low memory capacities. The main goal is to use both types of memory in such a way that their advantages are optimally exploited. The target is to allocate runtime-intensive code fragments with low memory requirements to the fast scratchpad memories. Previous approaches to separate program code on system memories consider the executed functions as the smallest logical unit. This is contradicted by the fact that not all parts of a function have the same computing time in relation to their memory usage. This article introduces a procedure that automatically analyses the compiled source code and identifies runtime intensive fragments. For this purpose, the translated code is executed in an offline simulator and the maximum repetition for each instruction is detected. This information is used to create logical code fragments called basic blocks. This is repeated for all functions in the overall system. During the analysis of the functions, the dependencies between them are also extracted and a corresponding call-graph with the call frequencies is generated. By combining the information from the call graph and the evaluation of the basic blocks, a prognosis of the computing load of the respective code blocks is created, which serves as base for the distribution into the fast scratchpad memories. To verify the described procedure, EEMBC’s CoreMark is executed on an Infineon AURIX TC29x microcontroller, in which different scratchpad sizes are simulated. It is demonstrated that the allocation of basic blocks scales significantly better with smaller memory sizes than the previous function-based approach.
Cite as

Philipp Jungklass and Mladen Berekovic. Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 3:1-3:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)

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@InProceedings{jungklass_et_al:OASIcs.NG-RES.2021.3,
  author =	{Jungklass, Philipp and Berekovic, Mladen},
  title =	{{Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout}},
  booktitle =	{Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
  pages =	{3:1--3:14},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-178-8},
  ISSN =	{2190-6807},
  year =	{2021},
  volume =	{87},
  editor =	{Bertogna, Marko and Terraneo, Federico},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.3},
  URN =		{urn:nbn:de:0030-drops-134790},
  doi =		{10.4230/OASIcs.NG-RES.2021.3},
  annote =	{Keywords: Memory Architecture, Memory Management, Real-time Systems}
}
Document
DOI: 10.4230/DagSemProc.10281.9
Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes

Authors: Matthias Hanke, Tim Kranich, Mladen Berekovic, and Yannis Papaefstathiou

Published in: Dagstuhl Seminar Proceedings, Volume 10281, Dynamically Reconfigurable Architectures (2010)

Abstract
Modern embedded systems have an emerging demand on high performance and low power circuits. Traditionally special functional units for each application are developed separately. These are plugged to a general purpose processors to extend its instruction set making it an application specific instruction set processor. As this strategy reaches its boundaries in area and complexity reconfigurable architectures propose to be more flexible. Thus combining both approaches to a reconfigurable application specific processor is going to be the upcoming solution for future embedded systems.
Cite as

Matthias Hanke, Tim Kranich, Mladen Berekovic, and Yannis Papaefstathiou. Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-7, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{hanke_et_al:DagSemProc.10281.9,
  author =	{Hanke, Matthias and Kranich, Tim and Berekovic, Mladen and Papaefstathiou, Yannis},
  title =	{{Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--7},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.9},
  URN =		{urn:nbn:de:0030-drops-28370},
  doi =		{10.4230/DagSemProc.10281.9},
  annote =	{Keywords: Reconfiguration, ASIP, RASIP, low power, high performance, video encoding, encryption, wireless sensor node, mobile device}
}
Document
DOI: 10.4230/DagSemProc.07041.7
Electrocardiogram on Wireless Sensor Nodes

Authors: Lennart Yseboodt, Michael De Nil, and Mladen Berekovic

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract
Wireless sensor nodes are applicable in a wide range of situations such as the medical, industrial or environmental domains, but the focus is on the biomedical domain. This paper presents the steps taken to develop a low power processor using Silicon Hive technology and mapping an electrocardiogram analysis algorithm on that processor. Today's energy-scavengers are able to deliver 100microwatt. This is the global power constraint of the sensor node. With a total power consumption of 16microwatt, the DSP processes the samples, compresses them into extracted parameters and the results are sent out by means of a radio.
Cite as

Lennart Yseboodt, Michael De Nil, and Mladen Berekovic. Electrocardiogram on Wireless Sensor Nodes. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-4, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{yseboodt_et_al:DagSemProc.07041.7,
  author =	{Yseboodt, Lennart and De Nil, Michael and Berekovic, Mladen},
  title =	{{Electrocardiogram on Wireless Sensor Nodes}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--4},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.7},
  URN =		{urn:nbn:de:0030-drops-11118},
  doi =		{10.4230/DagSemProc.07041.7},
  annote =	{Keywords: Ultra-low-power, electrocardiogram, wireless}
}
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