Abstract 1 Introduction 2 Preliminaries 3 A Theory of Parametric Bit-vectors 4 A Solver for Parametric Bit-vectors 5 Evaluation 6 Conclusion and Further Research References Appendix A Rewrite Rules of the Parametric Bit-Vector Rewriter 𝓡𝓦𝓑 Appendix B More Detailed Evaluation

Bit-Precise Reasoning with Parametric Bit-Vectors

Zvika Berger ORCID Bar-Ilan University, Ramat Gan, Israel Yoni Zohar ORCID Bar-Ilan University, Ramat Gan, Israel Aina Niemetz ORCID Stanford University, CA, USA Mathias Preiner ORCID Stanford University, CA, USA Andrew Reynolds ORCID The University of Iowa, Iowa City, IA, USA Clark Barrett ORCID Stanford University, CA, USA Cesare Tinelli ORCID The University of Iowa, Iowa City, IA, USA
Abstract

The SMT-LIB theory of bit-vectors is restricted to bit-vectors of fixed width. However, several important applications can benefit from reasoning about bit-vectors of symbolic widths, i.e., parametric bit-vectors. Recent work has introduced an approach for solving formulas over parametric bit-vectors, via an eager translation to quantified integer arithmetic with uninterpreted functions. The approach was shown to be successful for several applications, including the bit-width independent verification of compiler optimizations, invertibility conditions, and rewrite rules. We extend and improve that approach in several aspects. Theoretically, we improve expressiveness by defining a new theory of parametric bit-vectors that supports more operators and allows reasoning about the bit-widths themselves. Algorithmically, we introduce a lazy algorithm that avoids the use of uninterpreted functions and quantified axioms for them. Empirically, we show a significant improvement by implementing and evaluating our approach, and comparing it experimentally to the previous one.

Keywords and phrases:
Satisfiability Modulo Theories, Bit-precise Reasoning, Parametric Bit-vectors
Copyright and License:
[Uncaptioned image] © Zvika Berger, Yoni Zohar, Aina Niemetz, Mathias Preiner, Andrew Reynolds, Clark Barrett, and Cesare Tinelli; licensed under Creative Commons License CC-BY 4.0
2012 ACM Subject Classification:
Theory of computation Automated reasoning
; Software and its engineering Formal methods
Supplementary Material:
Other  (Zenodo): https://zenodo.org/records/15143242
Funding:
This research was supported in part by the Stanford Center for Automated Reasoning, the Stanford Center for Blockchain Research, Defense Advanced Research Projects Agency (DARPA) contract FA875024-2-1001, Israel Science Foundation (ISF) grant number 619/21, National Science Foundation (NSF) grant number 2303489, and a gift from Amazon Web Services.
Editors:
Jeremias Berg and Jakob Nordström

1 Introduction

Bit-precise reasoning as provided by Satisfiability Modulo Theories (SMT) for the theory of fixed-size bit-vectors [3] is a key requirement for a wide range of verification applications. In particular, it allows verification engines to reason about machine integers and hardware registers and supports a variety of operators (including arithmetic, bitwise, and word operators such as concatenation and extraction). It is also very useful for other theories, such as floating-point arithmetic and non-linear integer arithmetic, where reasoning over certain fragments of those theories can be reduced to reasoning in the theory of fixed-size bit-vectors [7, 17].

One of the biggest limitations of this theory is already evident in its name: it only allows reasoning about bit-vectors whose size (or, equivalently, width) is fixed. Thus, when declaring a bit-vector sort in the SMT-LIB language, its width must be specified as a numeral. This limitation poses a serious expressiveness issue: when a verification tool verifies a property using this theory of bit-vectors, the verification result is only valid for the explicitly specified bit-width(s). In the context of software verification, this means that some programs are proven correct in the presence of, say, 32-bit integer variables, but if their type is changed to 64-bit integers, the verification process has to be repeated. Similar issues occur during the development of specialized solvers for this theory, where much effort is dedicated to the design of rewrite rules and the generation of auxiliary lemmas [23, 34, 28, 31]. Before adding new rules or lemmas in the solver, it is valuable to be able to verify that they are correct, and their correctness is usually independent of bit-width. Being able to do so fast and automatically using SMT solvers (as opposed to following the lengthier process of developing interactive proofs [12, 19]) is highly beneficial for the development process. However, state-of-the-art SMT solvers do not currently support reasoning over bit-vectors of parametric size. Thus, it is common to verify the correctness of such rewrite rules and lemmas only for fixed bit-widths, from 1 up to some reasonably large value. This does not yield a proof of correctness in general although it increases confidence that the rules and lemmas are also correct for arbitrary bit-widths [28, 31].

Early work on bit-precise reasoning supported reasoning about parametric bit-vectors, but only for a small fragment of the theory (see, e.g., [35, 5, 15, 16]). In all cases, however, the supported fragment is not expressive enough for modern verification efforts.

More recently, an approach for solving formulas over parametric bit-vectors via an eager translation to quantified non-linear integer arithmetic with uninterpreted functions was proposed by Niemetz et al. [30, 29]. In that work, bitwise operators and the exponentiation function with base 2, which is required for translating arithmetic bit-vector operators to the integers, are axiomatized by means of uninterpreted functions and quantifiers. In particular, [30] introduced a theory of parametric bit-vectors where bit-widths are implicit, and so it is not possible to reason about then. The translation was implemented outside of an SMT solver and evaluated on three case studies: bit-width independent verification conditions for compiler optimizations [20], invertibility conditions [28], and rewrite rules [34]. In addition, since all three case studies only require reasoning about a single parametric bit-width, the implementation of the translation targets a fragment of the SMT-LIB theory of bit-vectors that does not involve multiple bit-widths. As a result, the possibility of verifying, e.g., compiler optimization reductions was limited, as it excluded optimizations involving bit-vector concatenations, extractions and extensions, all of which involve multiple bit-widths.

Later work [39] presented a translation of fixed-size bit-vectors to quantifier-free non-linear integer arithmetic with uninterpreted functions (coined int-blasting, generalizing earlier approaches, see, e.g., [38, 8, 6]) with the goal of improving the scalability of reasoning over large bit-vectors. Unlike [30], the approach of [39] is lazy, does not introduce any quantifiers and does not support reasoning over parametric bit-vectors. Further, it is integrated in cvc5 [1]. While not in general competitive with state-of-the-art bit-vector solvers, int-blasting showed promising performance improvements on problems involving large bit-widths arising from smart contract verification.

In this paper, we propose a procedure for reasoning about parametric bit-vectors based on the eager approach presented in [30]. Our technique extends and combines this eager approach with lazy techniques introduced for reasoning about fixed size bit-vectors via a reduction to the integers in [39]. In particular, we make the following contributions:

  1. (i)

    We introduce a theory of parametric bit-vectors with symbolic bit-widths as part of its signature. Our theory definition simplifies yet strengthens the theory of parametric bit-vectors introduced in [30] while enabling the reasoning over bit-widths.

  2. (ii)

    We present a lazy algorithm for determining satisfiability of parametric bit-vectors constraints that does not rely on quantifiers (as opposed to [30]) and generalizes the lazy handling of bitwise and from [39] to parametric bit-vectors. Additionally, instead of eagerly axiomatizing exponentiation with base 2 (as in [30]), we handle this operator lazily.

  3. (iii)

    We provide an implementation of a solver for parametric bit-vectors. The implementation is generic: it supports reasoning over arbitrary parametric bit-vector formulas (which goes beyond the prototype implementation presented in [30]). In particular, it fully supports reasoning over bit-widths, constraints on bit-vectors with multiple widths, and operators combining or returning bit-vectors of different widths, such as extraction, concatenation and extension.

  4. (iv)

    We evaluate our approach on a large and diverse set of benchmarks and show that our technique significantly improves over the eager approach introduced in [30].

For brevity and simplicity, and similarly to previous work [30, 39], our formal presentation focuses on quantifier-free formulas. We stress however, that our implementation fully supports quantifiers.111In fact, one of the benchmark sets in our experimental evaluation contains quantified formulas.

The remainder of this paper is organized as follows. In Section 2, we provide the necessary background on first-order logic. In Section 3, we present our definition for a theory of parametric bit-vectors. In Section 4, we describe our new solver for parametric bit-vectors. We provide a detailed evaluation of the solver in Section 5 and conclude with directions for future research in Section 6.

2 Preliminaries

We briefly review notions of many-sorted first-order theories with equality (see [13, 37] for more details). Let S be a set of sort symbols, and for every sort σS, let Xσ be an infinite set of variables of sort σ. We assume that sets Xσ are pairwise disjoint and define X as the union of sets Xσ. A signature Σ consists of a set ΣsS of sort symbols and a set Σf of function symbols. Arities of function symbols are defined in the usual many-sorted way. Constants are treated as nullary functions. We assume that Σ includes a Boolean sort 𝖡𝗈𝗈𝗅 and the Boolean constants (true) and (false). Function symbols whose return sort is 𝖡𝗈𝗈𝗅 are also called predicate symbols. We assume that for each sort σΣs, a binary equality predicate symbol σ is included in the signature. We will write just when σ is clear or not important.

We assume the usual definitions of well-sorted terms, literals, and formulas, and refer to them as Σ-terms, Σ-literals, and Σ-formulas, respectively. We include the ternary if-then-else operator iteσ of arity 𝖡𝗈𝗈𝗅×σ×σσ for each σΣs, and omit σ when it is clear from the context.

A Σ-interpretation maps: each σΣs to a distinct non-empty set of values σ (the domain of σ in ); each xXσ to an element xσ; and each fσ1σnσΣf to a total function f:σ1××σnσ if n>0, and to an element in σ if n=0. We use the usual inductive definition of the satisfiability relation between Σ-interpretations and Σ-formulas.

A theory T is a pair (Σ,I), where Σ is a signature and I is a non-empty class of Σ-interpretations that is closed under variable reassignment, i.e., if interpretation only differs from an I in how it interprets variables, then also I. Each interpretation I interprets 𝖡𝗈𝗈𝗅 as the two-element set {,} and σ as the identity relation over each sort σΣs. A Σ-formula φ is T-satisfiable (resp. T-unsatisfiable) if it is satisfied by some (resp. no) interpretation in I; it is T-valid if it is satisfied by all interpretations in I.

Table 1: Signature Σ𝐼𝐴 of the theory of integer arithmetic T𝐼𝐴.
Symbol SMT-LIB Syntax Arity
𝖨𝗇𝗍,𝖨𝗇𝗍 =, distinct 𝖨𝗇𝗍×𝖨𝗇𝗍𝖡𝗈𝗈𝗅
0,1,2, 0, 1, 2, … 𝖨𝗇𝗍
+,,,div,mod +, -, *, div, mod 𝖨𝗇𝗍×𝖨𝗇𝗍𝖨𝗇𝗍
,,<,> <=, >=, <, > 𝖨𝗇𝗍×𝖨𝗇𝗍𝖡𝗈𝗈𝗅

The theory T𝐼𝐴=(Σ𝐼𝐴,I𝐼𝐴) of integer arithmetic is defined as in the SMT-LIB 2 standard [2, 4]. Its signature Σ𝐼𝐴 is shown in Table 1 and includes a single sort 𝖨𝗇𝗍, function and predicate symbols {+,,,div,mod,<,,>,}, and a constant symbol for every integer value. Given a set of function symbols disjoint from those of Σ𝐼𝐴, the signature Σ𝐼𝐴() is obtained from Σ𝐼𝐴 by the addition of the symbols in . The theory T𝐼𝐴() consists of all Σ𝐼𝐴()-interpretations whose reduct to Σ𝐼𝐴 is a T𝐼𝐴-interpretation (i.e., the symbols in are freely interpreted). We may remove set braces when listing the elements of , e.g., by writing Σ𝐼𝐴(f,g) instead of Σ𝐼𝐴({f,g}).

3 A Theory of Parametric Bit-vectors

The SMT-LIB theory of bit-vectors TBV does not support parametric bit-vectors. Neimetz et al. [30] define a theory of parametric bit-vectors based on auxiliary functions (outside of the signature of the theory). These functions provide an implicit mapping from bit-vector variables to their symbolic bit-width and from symbolic parametric bit-vector constants to Σ𝐼𝐴-terms. A notion of admissibility is introduced to exclude mappings that assign non-standard interpretations (e.g., interpretations with zero or negative bit-widths). Furthermore, a parametric bit-vector formula is viewed as a class of fixed-size bit-vector formulas, i.e., a class of instances with concrete values for the bit-widths. This allows for a notion of well-sortedness based on the well-sortedness of these instances. As a consequence of relying on auxiliary mappings for symbolic bit-widths and constants, however, it is not possible to reason about bit-widths within that theory.

In the following, we introduce a new formal definition of the theory of parametric bit-vectors TPBV. As in [30], we have a single sort 𝖯𝖡𝖵 for bit-vectors of parametric size. Compared to that work, however, our definition of TPBV does not rely on meta-level functions to maintain well-sortedness constraints. Instead, we make symbolic bit-widths of parametric bit-vector terms explicit in the signature via the new operator || and introduce an explicit representation of parametric bit-vector constants via the conversion operator to-pbv. This enables reasoning about both parametric bit-vectors and their bit-widths within the theory.

3.1 Theory Definition

Table 2: Signatures ΣPBV and Σ𝐼𝐴(pow2,&), defined as extensions of signature Σ𝐼𝐴.
Symbol SMT-LIB Syntax Arity
ΣPBV = Σ𝐼𝐴 + the following operators
𝖯𝖡𝖵,𝖯𝖡𝖵 =,  distinct 𝖯𝖡𝖵×𝖯𝖡𝖵𝖡𝗈𝗈𝗅
<u, >u, <s, >s bvult,  bvugt,  bvslt,  bvsgt 𝖯𝖡𝖵×𝖯𝖡𝖵𝖡𝗈𝗈𝗅
u, u, s, s bvule,  bvuge,  bvsle,  bvsge 𝖯𝖡𝖵×𝖯𝖡𝖵𝖡𝗈𝗈𝗅
, bvnot,  bvneg 𝖯𝖡𝖵𝖯𝖡𝖵
&, , bvand,  bvor,  bvxor 𝖯𝖡𝖵×𝖯𝖡𝖵𝖯𝖡𝖵
<<, >>, >>a bvshl,  bvlshr,  bvashr 𝖯𝖡𝖵×𝖯𝖡𝖵𝖯𝖡𝖵
+, bvadd,  bvsub 𝖯𝖡𝖵×𝖯𝖡𝖵𝖯𝖡𝖵
, mod, div bvmul,  bvurem,  bvudiv 𝖯𝖡𝖵×𝖯𝖡𝖵𝖯𝖡𝖵
[:] pextract 𝖯𝖡𝖵×𝖨𝗇𝗍×𝖨𝗇𝗍𝖯𝖡𝖵
concat 𝖯𝖡𝖵×𝖯𝖡𝖵𝖯𝖡𝖵
extz pzero_extend 𝖨𝗇𝗍×𝖯𝖡𝖵𝖯𝖡𝖵
exts psign_extend 𝖨𝗇𝗍×𝖯𝖡𝖵𝖯𝖡𝖵
|| bvsize 𝖯𝖡𝖵𝖨𝗇𝗍
to-pbv int_to_pbv 𝖨𝗇𝗍×𝖨𝗇𝗍𝖯𝖡𝖵
Σ𝐼𝐴(pow2,&) = Σ𝐼𝐴 + the following operators
& piand 𝖨𝗇𝗍×𝖨𝗇𝗍×𝖨𝗇𝗍𝖨𝗇𝗍
pow2 pow2 𝖨𝗇𝗍𝖨𝗇𝗍

We define the theory of parametric bit-vectors TPBV as the pair (ΣPBV,IPBV), where the signature ΣPBV is the extension of Σ𝐼𝐴 described in Table 2. In addition to the integer sort 𝖨𝗇𝗍, its set of sort symbols includes a single, new sort 𝖯𝖡𝖵 for bit-vectors of parametric size. The set of function and predicate symbols of ΣPBV consists of parametric variants of a strict subset of the fixed-size bit-vector operators defined in SMT-LIB 2. This set of parametric bit-vector operators, however, is complete in the sense that it suffices to express parametric variants of the remaining bit-vector operators from SMT-LIB 2. Additionally, we introduce two new function symbols, || of arity 𝖯𝖡𝖵𝖨𝗇𝗍 and to-pbv of arity 𝖨𝗇𝗍×𝖨𝗇𝗍𝖯𝖡𝖵, in the signature.

In all the interpretations of IPBV, the domain of 𝖨𝗇𝗍 is the set of integer numbers, and the domain of 𝖯𝖡𝖵 is the set of all bit-vectors of all possible positive widths. The operators in Σ𝐼𝐴 are interpreted in the same way as in T𝐼𝐴. The new symbol || is interpreted as the function that maps each bit-vector x to its bit-width expressed as an integer. The new symbol to-pbv is interpreted as the function that maps any two integers n and m to the bit-vector of size n that represents mmod2n in binary notation if n>0, and to an arbitrary bit-vector otherwise. It can model constants of parametric bit-widths, e.g., to-pbv(k,0) represents the bit-vector that consists of k zeros when k0. Operator  is interpreted as the function that maps any two bit-vectors (of any two possible widths) to the bit-vector consisting of their concatenation. Operator [:] denotes the function that maps a bit-vector x, an integer i, and an integer j, in that order, to the bit-vector of width ij+1 that ranges from the j-th bit of x to the i-th bit of x (inclusive) if 0ji<|x|, and is interpreted arbitrarily otherwise. For a bit-vector x, we refer to the i-th bit of x as x[i], which abbreviates x[i:i]. We interpret x[0] as the least significant bit (LSB) and x[|x|1] as the most significant bit (MSB). Operators extz and exts take an integer and a bit-vector argument and are interpreted as in the SMT-LIB theory of fixed-size bit-vectors whenever the first argument (the number of added bits) is non-negative: the former extends the second argument with leading 0s, while the latter extends it with its most significant bit. If the number of added bits is negative, the interpretation is arbitrary. Operators and correspond to one’s and two’s complement. All other operators of ΣPBV are interpreted according to the following principle: if both operands have the same (positive) bit-width, then their interpretation is the same as in the theory of fixed size bit-vectors. Otherwise, the interpretation is arbitrary.

 Remark 1.

Recall that the signature of the theory of fixed-size bit-vectors TBV has a unique sort 𝖡𝖵(i) for each bit-width i{1,2,3,}. A more natural choice for a theory of parametric bit-vectors might then be the generalization of TBV to sorts of the form 𝖡𝖵(t) where t is an arbitrary integer term. However, this introduces the complication that syntactically distinct sort terms with equivalent integer arguments, such as 𝖡𝖵(1+3) and 𝖡𝖵(4) or 𝖡𝖵(x+x) and 𝖡𝖵(2x), would have to denote the same domain (bit-vectors of 4 bits) or domain family (bit-vectors of even bit-width). This exceeds the expressiveness of many-sorted logic where, in effect, distinct sorts denote disjoint domains. For this reason, we define a single sort 𝖯𝖡𝖵 to represent bit-vectors of all bit-widths. As a consequence, in our signature ΣPBV, terms can be well-sorted that do not match well-sorted terms in TBV. For example, the term x+y is well-sorted in our case even when x and y denote two bit-vectors of different bit-widths, something that is not permitted in the language of TBV. Thus, we establish restrictions on the interpretations of ΣPBV (described in Section 3.2) to have semantics that coincide with the semantics of the theory of fixed-size bit-vectors. In the example above, the restriction will be that x and y can only be interpreted as bit-vectors of the same width.

Note that parametric bit-vectors are expected to be supported more faithfully in the upcoming Version 3 of SMT-LIB, which is based on a higher-order logic with dependent types.

3.2 Satisfiability and Admissible Satisfiability

The way it is defined, theory TPBV contains non-standard interpretations as it has to account for terms like (xy)+x and formulas like xxx that are not well sorted in the theory of fixed-size bit-vectors. To address this laxness of TPBV’s sort system, we therefore define a notion of admissible TPBV-satisfiability that excludes such spurious interpretations. This definition relies on function Adm, defined in Algorithm 1. Function Adm collects width constraints while traversing over a given ΣPBV-term. It is defined via a function Bw as given in Algorithm 2, which constructs an integer term representing the symbolic bit-width of a parametric bit-vector term.

Definition 2.

Let φ be a ΣPBV-formula and a TPBV-interpretation. Let Adm be a function as defined in Algorithm 1. Interpretation  is admissible w.r.t. φ if Adm(φ). Formula φ is admissibly TPBV-satisfiable if it is satisfied by a TPBV-interpretation that is admissible w.r.t. φ.

Thus, a formula φ is admissibly TPBV-satisfiable only if it is satisfied by an admissible TPBV-interpretation . We require that an admissible interpretation  assign bit-widths to ΣPBV-terms in φ while satisfying the admissibility condition described by the function Adm defined in Algorithm 1.

Algorithm 1 Function Adm to recursively construct admissibility constraints. Symbol z denotes constants of sort 𝖨𝗇𝗍 and x constants of sort 𝖯𝖡𝖵. Symbol ranges over symbols of Σ𝐼𝐴, Boolean connectives, and ite𝖨𝗇𝗍. Symbol ranges over symbols in ΣPBV not explicitly handled otherwise.
Algorithm 2 Function Bw to compute the bit-width of 𝖯𝖡𝖵-terms. Symbol x denotes variables of sort 𝖯𝖡𝖵. Symbol ranges over the symbols of ΣPBV of sort 𝖯𝖡𝖵 not explicitly handled otherwise.
Example 3.

Consider a formula φ given as yzw. The admissibility condition Adm(φ) is determined as |y||z|+|w||y|>0|z|>0|w|>0. An admissible TPBV-interpretation satisfying φ is given by y=00, z=0 and w=0. Thus, φ is admissibly TPBV-satisfiable. Now, consider formula φ given as xx+(xx). Its admissibility condition Adm(φ) is defined as |x||x||x|>0|x||x|+|x| (after simplifications), which is TPBV-unsatisfiable. That is, there exists no admissible TPBV-interpretation for φ and, thus, φ is not admissibly TPBV-satisfiable. However, φ is TPBV-satisfiable: consider a TPBV-interpretation , given by x=0. Then, (xx) is the bit-vector 00. Since x and xx do not have the same bit-width, may interpret x+(xx) arbitrarily, and so we can set (x+(xx)) to be again the bit-vector 0. We then get that satisfies φ.

Note that our notion of admissibility corresponds to the notion of admissibility introduced by Niemetz et al. [30]. However, its definition differs in one key aspect. In [30], admissibility was enforced by using auxiliary functions and by instantiating parametric bit-vector formulas for all possible fixed bit-widths via universal quantification over the parametric bit-widths. Bit-widths and mappings from PBV-constants to Σ𝐼𝐴-terms were implicit in the signature, whereas in our definition of ΣPBV, we explicitly include operators || and to-pbv. This allows us to explicitly define admissibility conditions and to reason about symbolic bit-widths in ΣPBV-formulas.

4 A Solver for Parametric Bit-vectors

In this section, we describe a solver for admissible TPBV-satisfiability. Its main component is the translation of ΣPBV-formulas to formulas over a signature Σ𝐼𝐴(pow2,&). As defined in Table 2, signature Σ𝐼𝐴(pow2,&) extends Σ𝐼𝐴 with two new function symbols, pow2 and &.

We define a theory T𝐼𝐴(pow2,&) over Σ𝐼𝐴(pow2,&), where symbols pow2 and & are interpreted arbitrarily. Additionally, for the purpose of the translation, we consider a theory T𝐼𝐴(pow2,&) over Σ𝐼𝐴(pow2,&) in which the interpretation of pow2 and & is fixed and defined as follows. The term pow2(n) is interpreted as the n-th power of 2 whenever n is non-negative, and as 0 otherwise. The interpretation of &(k,a,b) is defined as follows. If k>0 and a,b{0,,2k1}, then &(k,a,b) is the integer that corresponds to performing a bitwise conjunction on the unsigned bit-vector representations of a and b. That is, let a,b be the unsigned bit-vector representations of a and b of width k, then the interpretation of &(k,a,b) is defined as Σi=0k1a[i]b[i]2i. If k>0 and a,b{0,,2k1}, then the interpretation of &(k,a,b) is the same as &(k,amod2k,bmod2k). If k0, then its interpretation is 0.

 Remark 4.

Notice that pow2 is defined over the integers. Thus, we always interpret a negative exponent n as 0, as this is consistent with truncating the integer division in 2n12n towards zero. Further, notice that & defines a special case for bit-width k0. Our translation will never produce Σ𝐼𝐴(pow2,&)-formulas that are satisfiable due to these corner cases because it ensures that: (1) the exponents of pow2 are integer terms representing bit-widths and (2) integer terms that represent bit-widths are always positive. In fact, for our purposes, the special cases mentioned above could also be interpreted arbitrarily. We choose a fixed interpretation since it is easier to implement.

Starting with a ΣPBV-formula, we first simplify the formula by applying rewrite rules 𝒲, as described in Section 4.1. The rewritten ΣPBV-formula is then translated to a Σ𝐼𝐴(pow2,&)-formula using function Trans, as described in Section 4.2. Finally, the T𝐼𝐴(pow2,&)-satisfiability of the resulting Σ𝐼𝐴(pow2,&)-formula is determined via procedure Solve , described in Section 4.3.

4.1 The Parametric Bit-Vector Rewriter 𝓡𝓦𝓑

State-of-the-art SMT solvers rely heavily on simplification techniques that are applies as a preprocessing step, before the main solver process begins. One such technique is based on term rewriting. For the theory of fixed-size bit-vectors (for which the dominant solving technique is bit-blasting, an eager reduction to propositional logic), SMT solvers implement hundreds of rewrite rules. However, rewrite rules for TBV that target bit-blasting are not necessarily beneficial for alternative solving procedures. In particular, they may not be useful for our TPBV procedure, which relies on a translation to integer arithmetic. Thus, some care is required in selecting rewrite rules for our procedure.

We implemented a set of rewrite rules for TPBV based on rewrite rules for TBV as implemented in the SMT solver cvc5 [1]. Rewrite rules implemented in cvc5 are documented in the domain-specific language RARE [33], which allows for easy adoption and lifting to TPBV. We selected TBV-rewrite rules for lifting to TPBV based on the following principles: (i) a rewrite rule should not introduce a bitwise operator; (ii) the translation of the rewritten formula to the integers should not have more occurrences of operators mod and pow2 than the original one. These principles are based on the fact that state-of-the-art solvers for integer arithmetic do not support bitwise operations over integers, and also offer very limited support for exponentiation. Further, mod is non-linear and one of the most expensive operations for integer arithmetic procedures. Interestingly, following these guiding principles, some TBV-rewrite rules are useful for TPBV when applied in the opposite direction.

The rewrite rules that we have implemented are presented in Appendix A.

Example 5.

Consider a TBV-rule that rewrites (x&y)[i:j] to (x[i:j])&(y[i:j]). This is useful for bit-blasting since it reduces the size of the bit-level representation. However, for our translation to integer arithmetic, extractions are expensive as they introduce div, mod and pow2 terms. Thus, we did not lift this rule to TPBV but included its right-to-left variant in 𝒲 instead.

4.2 The Translation Function Trans

Algorithm 3 Translation function Trans and conversion function Conv. We use x for 𝖯𝖡𝖵 variables, z for 𝖨𝗇𝗍 variables, 𝗎𝗍𝗌(k,z) for 2(zmodpow2(k1))z, for any operator in {<,,>,}, and for ite, logical connectives and symbols in Σ𝐼𝐴.

After obtaining the rewritten ΣPBV-formula φ, we translate it into a Σ𝐼𝐴(pow2,&)-formula φ such that φ is admissibly TPBV-satisfiable iff φ is T𝐼𝐴(pow2,&)-satisfiable. The translation function Trans is given in Algorithms 3 and 4. It is based on the one in [30], with changes underlined.

Prior to the actual conversion step, ΣPBV-formula φ is augmented, conjunctively, with the admissibility constraints Adm(φ), constructed as described in Algorithm 1, as well as the range and size constraints Range(φ). The latter are defined over integer constants that represent either parametric bit-vector constants or symbolic bit-widths, as described in Algorithm 4. The latter traverses the formula and adds constraints for the range of the integer terms representing bit-vector terms, according to their original bit-widths.

The augmented ΣPBV-formula is then converted via function Conv into an equisatisfiable Σ𝐼𝐴(pow2,&)-formula as defined in Algorithm 3.

We assume a one-to-one mapping χ from variables of sort 𝖯𝖡𝖵 to variables of sort 𝖨𝗇𝗍, as well as a one-to-one mapping κ from 𝖯𝖡𝖵-terms to variables of sort 𝖨𝗇𝗍, such that their images are disjoint. Intuitively, χ translates variables of sort 𝖯𝖡𝖵 to corresponding variables of sort 𝖨𝗇𝗍 while κ translates terms of the form |t| to fresh integer variables representing the size of the parametric bit-vector term t. Compared to our previous work [30], our new translation handles the new operators || and to-pbv, improves the encodings of the operators >>, , and to eliminate applications of mod, and adds support for the operators [:], exts, and extz. Notice that the encoding of >>a is not explicitly described, as that operator can be expressed in terms of >> and ite.

Following Zohar et al. [39], we do not handle and natively. Instead, we eliminate them by means of &, + and , based on the following identities derived from [18]: xy(x+y)(x&y) and xy(xy)(x&y). This elimination is embedded in the translation function and improves upon the original elimination in [39] by avoiding the introduction of additional mod operations.

Algorithm 4 Function Range to recursively construct size and range constraints. We use x for 𝖯𝖡𝖵 variables, z for 𝖨𝗇𝗍 variables, and for ite, logical connectives and symbols in ΣPBV.
Example 6.

Consider again the formula φ:=yzw from Example 3. Then, Trans(φ)=Conv(φRange(φ)Adm(φ)). Now, Conv(φ) is yzpow2(kw)+w, where y=χ(y), z=χ(z), w=χ(w), and kw=κ(w). Further, Conv(Range(φ)) is 0y<pow2(ky)0z<pow2(kz)0w<pow2(kw), where ky=κ(y) and kz=κ(z). The result of Adm(φ) is given in Example 3, and then Conv replaces |y|, |z|, and |w| by ky, kz, and kw, respectively.

Our translation function Trans makes heavy use of mod and pow2 operations. In practice, some of these applications can be safely eliminated to optimize the encoding. For example, consider the term (x+x)+x, where κ(x)=k. The result of Conv on this term is (((x+x)mod2k)+x)mod2k, where x=χ(x). Instead, we directly translate it to ((x+x)+x)mod2k.

4.3 The 𝑻𝑰𝑨(𝐩𝐨𝐰2,&)-Solver

After translating a ΣPBV-formula to a Σ𝐼𝐴(pow2,&)-formula, we check if it is T𝐼𝐴(pow2,&)-satisfiable with a dedicated CEGAR-style procedure Solve , which iteratively refines over-approximations of pow2 and & as given in Algorithm 5. This procedure takes an approach similar to the incremental linearization of non-linear arithmetic constraints [9, 10]. It relies on a set of quantifier-free lemmas which fully specify the semantics of operators pow2 and &. The set is constructed by instantiating the (implicitly) universally quantified lemma schemas pow2, shown in Table 3, and &, shown in Table 4, for all pow2-terms and &-terms in φ. The instantiations of the lemmas also depend on the values of variables in the current interpretation . Note that when computing the instantiation for pow2-lemmas, we also include pow2-terms occurring in lemmas for &.

The procedure further assumes the availability of a subprocedure Solve to determine the T𝐼𝐴(pow2,&)-satisfiability of a set of Σ𝐼𝐴(pow2,&)-formulas Γ. Recall that in T𝐼𝐴(pow2,&), symbols pow2 and & are uninterpreted and thus, Γ is an over-approximation of φ in T𝐼𝐴(pow2,&). If Solve determines the unsatisfiability of Γ, we conclude with “unsat”. If it determines its satisfiability, we conclude with “sat” only if the resulting interpretation also satisfies all lemmas in . Otherwise, we refine Γ by adding to it all lemmas that are not satisfied by .

Algorithm 5 Procedure for T𝐼𝐴(pow2,&)-satisfiability. We assume Solve is a procedure for T𝐼𝐴(pow2,&)-satisfiability that returns “sat” or “unsat” and an interpretation for satisfiable formulas. For a set X, 𝑇𝑒𝑟𝑚𝑠(X) denotes the set of terms occurring in X.

The set pow2 in Table 3 includes 4 lemma schemas from [30], which describe basic properties of the pow2 operator. In addition, we consider the following three new lemmas. Lemma neg considers negative inputs, for which pow2 is defined to be interpreted as 0 in T𝐼𝐴(pow2,&). Lemma bound strengthens a lemma from recent work proposing a CEGAR-style approach for a new SMT theory for integer arithmetic with exponentiation [14]. From there, we get that when x3, then 2x+1 is a lower bound for pow2(x). We notice that when x7, we have 2x2 as a tighter lower bound. In order to avoid non-linear multiplications, we linearize this bound via concrete values v=x. We further include instances of value with v=x, to block concrete model values.

The set of lemma schemas & in Table 4 includes 8 lemmas that were introduced in [30] and capture basic properties of the & operator. In addition, we consider 4 lemmas that did not appear in [30]. Lemma empty captures the corner case when the bit-width is non-positive. Lemmas lsb and one capture the cases where one of the arguments is even or 1. Note that due to lemma sym, it is sufficient to consider only one variant of each lemma. Lemma sum is based on the fact that for a fixed bit-width n, &(n,x,y) is defined as Σi=0n1𝖾𝗑i(x)𝖾𝗑i(y)2i, with 𝖾𝗑i(x) defined as (xdiv2i)mod2 as in Table 4. We observe that for a bit-width mn with 0x<2n and 0y<2n, the equation &(m,x,y)&(n,x,y) holds – consider, for example, &(5,1,1)&(4,1,1). Lemma sum is a generalization of this observation. It is instantiated with v=k.

Example 7.

Consider the formula x&xx. Its translation will be &(k,x,x)xmodpow2(k), with the addition of the appropriate admissibility and range constraints. Then lemma div will be instantiated in set as k0kdivpow2(k)0. Lemma min will be instantiated as x0&(k,x,x)0. In contrast, the approach of [30] introduces the universal closure of such lemmas, instead of specific instantiations.

Note that procedure Solve resembles the lazy approach of [39], with several key differences. First, since we are dealing with parametric bit-widths, our algorithm does not necessarily terminate, as the set of possible bit-widths is unbounded. Second, our algorithm not only lazily handles operator &, but also pow2. Operator pow2 did not occur when int-blasting in [39] since there, all exponents were concrete constants. Thus, exponentiation was simply evaluated. Finally, our sets of lemmas for & and pow2 expand both the axioms from [30] and the lemmas from [39].

Table 3: The set of lemma schemas defined by pow2(S,), over a set of pow2-terms S and an interpretation . The variables x and y in the formulas above are instantiated for each pow2-term in S. Symbol v is a schema variable standing for an arbitrary numeral. It is instantiated with v:=x.
Name Lemma Schema Source
pow2(x)S
positive x0pow2(x)>0 [30]
even x1pow2(x)mod20 [30]
div x0xdivpow2(x)0 [30]
neg x<0pow2(x)0 new
bound (7vvx)vx+v2<pow2(x) new
value (0xxv)pow2(x)2v new
pow2(x)S, pow2(y)S
monotonicity (0xx<y)pow2(x)<pow2(y) [30]
Table 4: The set of lemma schemas defined by &(S,) over a set of &-terms S. The variables k, x, z, and w in the formulas above are instantiated for each &-term in S. We use the expression tk to denote 0t<pow2(k), the expression min(x,y) to abbreviate ite(x<y,x,y), and 𝖾𝗑i(x) for (xdiv2i)mod2. Symbol v is a schema variable standing for an arbitrary numeral. It is instantiated with v:=k.
Name Lemma Schema Source
&(k,x,y)S
base (k>0x1y1)&(k,x,y)1 [30]
max (k>0xkypow2(k)1)&(k,x,y)x [30]
min y0&(k,x,y)0 [30]
idem (k>0xkxy)&(k,x,y)x [30]
contra (x+y)modpow2(k)pow2(k)1&(k,x,y)0 [30]
range 0x0y0&(k,x,y)min(x,y) [30]
empty k0&(k,x,y)0 new
lsb xmod20&(k,x,y)mod20 new
one (k>0y1)&(k,x,y)xmod2 new
sum (kvv>0xvyv)&(k,x,y)Σi=0v1𝖾𝗑i(x)𝖾𝗑i(y)2i new
&(k,x,z)S, &(k,y,w)S
sym (xwyz)&(k,x,y)&(k,z,w) [30]
diff (k>0zwxyxkykzk)(&(k,x,z)y&(k,y,w)x) [30]

Putting all components described in this section together, we obtain an incomplete but sound procedure Solve (Trans(𝒲(φ))) for admissible TPBV-satisfiability.

Theorem 8.

Let φ be a ΣPBV-formula and let φ=Trans(𝒲(φ)). If Solve (φ) terminates, then φ is admissibly TPBV-satisfiable if and only if Solve (φ) returns “sat”.

4.4 Proof of Theorem 8

The correctness argument for Theorem 8 is similar to those from [30, 39]: assuming a TPBV-interpretation that satisfies a ΣPBV-formula φ, while also being admissible w.r.t. φ, we can construct a T𝐼𝐴(pow2,&)-interpretation that satisfies the translation of φ, as well as the relevant lemmas from Tables 3 and 4, and vice versa. Compared to [30], the auxiliary admissibility condition that was assumed is now replaced by the satisfaction of Adm(φ). What is left to show is:

  1. 1.

    The new translation of >> is correct.

  2. 2.

    The eliminations of and are correct.

  3. 3.

    The treatment of extraction and extensions is correct.

  4. 4.

    The rules of the 𝒲 rewriter are TPBV-valid.

  5. 5.

    All lemmas of Tables 3 and 4 are T𝐼𝐴(pow2,&)-valid.

We prove the first item in Section 4.4.1 and the second in Section 4.4.2. The third follows directly from the SMT-LIB standard. For the fourth, notice that we only use rewrite rules that are already used in cvc5 and are bit-width independent. For their correctness proofs, see, e.g., [19]. For the fifth, most lemmas are taken from [30]. Of the new lemmas that we add, correctness is trivial for lemmas neg, value, empty, lsb and one. We prove the correctness of the remaining lemmas in Section 4.4.3.

4.4.1 Correctness of Translation of >>

It suffices to show that in every T𝐼𝐴(pow2,&)-interpretation that satisfies the formulas Conv(x)0, pow2(Conv(y))>0, and pow2(k)>Conv(x), the expressions Conv(x)divpow2(Conv(y)) and (Conv(x)divpow2(Conv(y)))modpow2(k) are interpreted the same. This holds, as every such interpretation also satisfies Conv(x)divpow2(Conv(y))Conv(x)<pow2(k).

4.4.2 Correctness of Elimination of | and

We start with the following lemma:

Lemma 9.

Suppose k>0, x0 and y<2k. Then, 0x+y&(k,x,y)<2k and 0x+y2&(k,x,y)<2k.

Proof.

In this proof we treat & and pow2 as arithmetic operators with a fixed interpretation as given to them by all T𝐼𝐴(pow2,&)-interpretations. This saves us from superscripting interpretations to these symbols, which is not needed since their interpretations are fixed. We consider the required inequalities separately:

  • 0x+y&(k,x,y)<2k:

    1. 1.

      By the semantics of &, we have &(k,x,y)x. Since y0, we get &(k,x,y)x+y. Therefore, x+y&(k,x,y)0.

    2. 2.

      Next, we show x+y&(k,x,y)<2k. Since 0x,y<2k, we have: x=Σi=0k12i𝖾𝗑i(x) and y=Σi=0k12i𝖾𝗑i(y), where for every z, 𝖾𝗑i(z)=(zdiv2i)mod2. By the semantics of &, we have &(k,x,y)=Σi=0k12iite(𝖾𝗑i(x)=𝖾𝗑i(y)=1,1,0). Notice that we can also have y=Σi=0k12iite(𝖾𝗑i(x)=𝖾𝗑i(y)=1,1,0)+Σi=0k12iite(𝖾𝗑i(x)=0𝖾𝗑i(y)=1,1,0).

      Now, we clearly have that x+y&(k,x,y) equals Σi=0k12i𝖾𝗑i(x)+Σi=0k12iite(𝖾𝗑i(x)=𝖾𝗑i(y)=1,10)+Σi=0k12iite(𝖾𝗑i(x)=0𝖾𝗑i(y)=1,1,0)Σi=0k12iite(𝖾𝗑i(x)=𝖾𝗑i(y)=1,1,0), which is: Σi=0k12i𝖾𝗑i(x)+Σi=0k12iite(𝖾𝗑i(x)=0𝖾𝗑i(y)=1,1,0). This is equal to Σi=0k12iite(𝖾𝗑i(x)=1,1,0)+Σi=0k12iite(𝖾𝗑i(x)=0𝖾𝗑i(y)=1,1,0). Clearly, this must be at most Σi=0k12iite(𝖾𝗑i(x)=1,1,0)+Σi=0k12iite(𝖾𝗑i(x)=0,1,0), which equals Σi=0k12i, which must be strictly smaller than 2k.

  • 0x+y2&(k,x,y)<2k:

    1. 1.

      By the semantics of &, we have &(k,x,y)x and &(k,x,y)y. Therefore, x+y2&(k,x,y), and so x+y2&(k,x,y)0.

    2. 2.

      For the other direction, since &(k,x,y)0 for all k,x,y, we have: x+y2&(k,x,y)x+y&(k,x,y). By the inequality item, x+y&(k,x,y)<2k.

We now justify the elimination of operator and , relying on the following equations from [18]:

x+y(x&y)+(xy)(1)
xy(xy)(x&y)(2)

For , we get get: xy(x+y)(x&y). Translating the right-hand side of this equation to integer arithmetic with &, we get ((x+y)mod2k(&(k,x,y)))mod2k, where k is the bit-width of x and y. This can be simplified to ((x+y)(&(k,x,y)))mod2k. In order to show an equality to ((x+y)(&(k,x,y))), which is our actual translation, it is left to show that 0((x+y)(&(k,x,y)))<2k, as stated in the first item of Lemma 9.

The justification for the elimination of operator is similar. Combining (1) and (2), we get that xy((x+y)(x&y))(x&y) and thus xyx+y(2x&y). Translating the right-hand side of this equation to integer arithmetic with &, we get ((x+ymod2k)(2&(k,x,y)mod2k))mod2k, which can be simplified to (x+y2&(k,x,y))mod2k. To prove that this is the same as (x+y2&(k,x,y)), it suffices to prove that 0(x+y2&(k,x,y))<2k, as stated in the second item of Lemma 9.

4.4.3 Correctness of Lemmas

The following lemmas prove the validity of our lemmas bound and sum.

Lemma 10.

Suppose v7. Then xvvx+v2<pow2(x).

Proof.

We first prove that x72x2<2x by induction on x. If x=7 then this trivially holds. Assume that this holds for some x. Then, 2(x+1)2=2x2+4x+2. By the induction hypothesis, 2x2<2x. Also, 4x+2<2x2<2x when x7. Hence we get 2(x+1)2<2x+1. Let v7 and suppose xv. Then, vxx2 and v2x2, and so vx+v22x2<2x.

Lemma 11.

If kv>0 then (xvyv)&(k,x,y)Σi=0v1𝖾𝗑i(x)𝖾𝗑i(y)2i.

Proof.

We always have &(k,x,y)Σi=0k1𝖾𝗑i(x)𝖾𝗑i(y)2i. Since kv and 0x,y<2v, we have that 𝖾𝗑i(x)=𝖾𝗑i(y)=0 for every vik1, and thus 𝖾𝗑i(x)𝖾𝗑i(y)2i=0.

5 Evaluation

We have implemented our approach by extending two tools: the generic SMT solver API smt-switch [21] and the SMT solver cvc5 [1]. In smt-switch, we extended the SMT-LIB parser with support for parsing ΣPBV-formulas, and implemented our rewriter 𝒲 (Section 4.1) and the translation Trans (Algorithm 3). In cvc5, we implemented our procedure Solve (Algorithm 5) by extending cvc5’s non-linear arithmetic module with two subsolvers to lazily handle pow2 and &. The subsolver for & generalizes the &-subsolver in [39], which was only able to reason over & with fixed bit-widths, by allowing reasoning over symbolic bit-widths.

Note that the handling of ΣPBV-formulas and their translation is entirely implemented in smt-switch. Externalizing the ΣPBV-translation pipeline enables the use of our approach in combination with other back-end solvers that support reasoning over pow2 and & operators.

5.1 Benchmarks

The SMT-LIB standard [2, 4] does not yet define a theory for parametric bit-vectors. Consequently, benchmarks encoding problems over parametric bit-vectors are not yet part of the SMT-LIB benchmark library. Thus, we evaluate our techniques utilizing a wide range of benchmark sets, originating from various sources, as detailed below.

alive (200 benchmarks).

Set alive consists of verification conditions for compiler optimizations that are generated by Alive [20]. The evaluation of [30] included 180 such conditions. Here, we include 20 additional conditions that were not supported by the implementation of [30]. Among the new conditions, 17 involve multiple bit-widths and 3 include terms of the form to-pbv(k,k), representing a bit-vector of length k whose unsigned integer value is k.

ic (180 benchmarks).

Set ic consists of benchmarks to verify the correctness of the invertibility conditions formalized in Niemetz et al. [27], which utilizes them for quantifier instantiation. They are also instrumental to the local search procedure of [27]. The evaluation of [30] included correctness checks for 160 out of 180 conditions. Here, we add the remaining 20 checks that encode invertibility conditions over concatenation, which were not supported by the implementation of [30].

rewrite (1500 benchmarks).

Set rewrite consists of the bit-width independent correctness checks of rewrite rule candidates for the theory of fixed-size bit-vectors considered in [30]. They were automatically generated using CVC4SY [36], a Syntax-Guided Synthesis (SyGuS) engine.

syrew (1500 benchmarks).

Set syrew consists of bit-width independent versions of the equivalence checks of TBV-terms from [31], which were enumerated by the SyGuS engine of cvc5. There, these checks were instantiated for large bit-widths to evaluate the performance of TBV-solvers.

lemmas (70 benchmarks).

Set lemmas, also originating from [31], consists of 70 refinement lemmas describing properties of arithmetic bit-vector operators for a CEGAR-style procedure for TBV implemented in the SMT solver Bitwuzla [25]. These lemmas were verified to be correct up to bit-width 256 [31] but are required to be correct for arbitrarily large bit-widths. This benchmark set encodes bit-width independent correctness checks of these lemmas. Note that two benchmarks involve multiple bit-widths, and thus cannot be handled by the implementation of [30].

icfb (46 benchmarks).

Set icfb originates from a local search procedure [24] that generalizes the technique from [27] and defines invertibility conditions (and conditions for a weaker notion of invertibility called consistency) over ternary bit-vectors. These conditions were verified to be correct up to bit-width 65 but are required to hold for any bit-width. This benchmark set consists of bit-width independent correctness checks of the conditions, of which 16 benchmarks involve multiple bit-widths. Note that some conditions cannot be encoded to TPBV due to the occurrence of bit-width dependent functions that require counting, e.g., the counting of leading zeroes, and were thus excluded from this set. Further note that in the original publication [24], one of the invertibility conditions for operator <u was given incorrectly (the implementation and verification of the rule used the correct definition) [26]. We include both versions for this condition.

mut (9442 benchmarks).

The majority of the benchmarks in the sets above are unsatisfiable. For a more thorough evaluation on satisfiable benchmarks, we created a benchmark set mut by mutating the benchmarks from the other sets. This realistically mimics the introduction of bugs in verification conditions, e.g., by using a bitwise disjunction instead of conjunction. Let (f,g) be a pair of ΣPBV-terms or function symbols with the same arity, and let φ be a ΣPBV-formula in which f occurs. A mutation of φ is obtained from (f,g) by replacing the first occurrence of f by g. We generated mutations for pairs (f,g){(&,),(+,),(,),(<<,>>),(to-pbv(k,1),to-pbv(k,0)),(to-pbv(k,k),to-pbv(k,0))} and their permutations (g,f), and filtered out duplicates.

Table 5: Configurations considered in our experimental setup.
Feature Baseline Eager Pbv
Target Theory T𝐼𝐴(pow2,&,,) T𝐼𝐴(pow2,&) T𝐼𝐴(pow2,&)
Multiple Bit-widths
Lazy pow2
Lazy &
-elimination
-elimination
>> without mod
New lemmas for &
New lemmas for pow2
No redundant axioms
𝒲
mod-reduction

5.2 Experimental Setup

For our experimental evaluation, we consider three configurations: configuration Baseline, which corresponds to the best configuration of [30]; configuration Pbv, which implements our techniques as described in Section 4; and configuration Eager, which corresponds to extending configuration Baseline with our rewriter 𝒲 and optimizations as detailed in Table 5, while still handling operators pow2 and & eagerly. Recall that the implementation of [30] utilized translations that were tailored to each considered benchmark set, which does not allow a faithful comparison to our Pbv-configurations. Thus, we reimplemented the best configuration comb from [30] as configuration Baseline in our tool. This not only allows us to evaluate Baseline on a larger benchmark set, but also ensures a fair comparison since all configurations use the same underlying cvc5 version as well as the same infrastructure for parsing, manipulating and solving formulas.

Table 5 outlines the differences between the configurations. The features considered for each configuration are listed in the first column. Target Theory specifies the underlying theory (e.g., whether pow2 and & are uninterpreted or not). Accordingly, Lazy pow2 and Lazy & determine whether these operators are handled lazily or eagerly. For uninterpreted functions, we use quantified axiomatizations, and No redundant axioms determines whether these axiomatizations are always added to the input formula, regardless of whether the axiomatized operator occurs in the formula. Multiple Bit-widths corresponds to supporting multiple bit-widths in the same formula. -elimination and -elimination denote the elimination of and in the translation (as described in Section 4.2). The usage of an optimization to the translation of >>, which eliminates a mod operation (as shown in Algorithm 3), is determined by >> without mod. New lemmas for & and New lemmas for pow2 correspond to the usage of the new lemmas from Tables 3 and 4. 𝒲 determines whether rewriter 𝒲 from Section 4.1 is enabled, and mod-reduction determines whether some optimizations that eliminate nested mod in arithmetic operators are applied, as mentioned in Section 4.2.

Configurations Baseline and Eager rely on an eager translation. They introduce uninterpreted functions that are axiomatized by means of quantified formulas that are added as preamble to each translation. In contrast, configuration Pbv employs a translation to theory T𝐼𝐴(pow2,&), which does not rely on quantifiers and handles operators pow2 and & lazily. Further, configuration Baseline does not support multiple bit-widths in the same formula. Configuration Eager, on the other hand, incorporates several optimizations over Baseline, including the new lemmas, that are also incorporated in Pbv. Notice that operators and are handled natively in configuration Baseline, while configurations Eager and Pbv use elimination rules for them. In Appendix B, we include an extended set of results with 14 more configurations.

 Remark 12.

Even though our evaluation includes benchmark sets from the evaluation in [30], the numbers are not directly comparable due to the following reasons. Each benchmark in set ic describes an equivalence, which was split into two implications in [30]. Additionally, conditional inverses were introduced there, and were incorporated into the benchmarks with the main goal of proving invertibility conditions as correct. Benchmark set rewrite was solved in a semi-automated and iterative manner: whenever a rewrite candidate was proven correct, it was included as an axiom in the benchmarks to prove. In this evaluation, we refrain from such interventions, as our goal is to measure how efficient our approach is in a fully automated setting. Further, the translation of [30] utilized quantifier-specific optimizations and included instantiation patterns as well as concrete instantiations for some of the axioms. However, such patterns are often tailored to a specific solving procedure, and concrete instantiations are only sound for unsatisfiable benchmarks (which was the focus of [30]). In configuration Baseline, we do not use any of these optimizations.

We ran our experiments on a cluster of 22 machines equipped with Intel Xeon Gold 6348 CPUs. For each solver and benchmark pair, we used a CPU time limit of 60 seconds and a memory limit of 8GB. Preliminary experiments showed that the difference in results with higher time limits were not significant. Also, no configuration exceeded the memory limit of 8GB during solving.

5.3 Results

Table 6 summarizes the results for each benchmark set described in Section 5.1, over the configurations introduced in Section 5.2, as well as the virtual best solver over these configurations in column VBS.

Table 6: Overall number of solved benchmarks for each configuration. VBS corresponds to the virtual best solver over all three configurations. Time is the penalized runtime, counting unsolved instances as timeout.
Benchmarks # Baseline Eager Pbv VBS
alive 200 71 93 107 124
ic 180 43 58 77 81
rewrite 2006 658 1221 1331 1382
syrew 1500 558 720 912 951
lemmas 70 12 14 23 23
icfb 46 1 9 12 12
mut 9441 669 1084 4863 4915
total 13443 2012 3199 7325 7488
sat 0 0 3641 3641
unsat 2012 3199 3684 3847
unique 24 57 4222 4303
time [seconds] 709k 634k 375k 355k

Overall, configuration Pbv significantly outperforms Baseline and Eager in number of solved instances and runtime. Comparing Pbv against Eager indicates that using a lazily handling pow2 and & is superior to the quantifier-based eager approach. Comparing Eager against Baseline shows that the optimizations discussed in Section 4 are beneficial for the eager translation as well. On the 1863 instances commonly solved by all three configurations, Eager is almost 4 times faster than Baseline while Pbv is more than 12 times faster than Eager. On the 3060 instances commonly solved by Eager and Pbv, configuration Pbv is more than 18 times faster. Notice that configurations Baseline and Eager do not solve any satisfiable benchmarks, due to the usage of quantified axiomatizations. In fact, the presence of these axiomatizations already prevents both Baseline and Eager from reporting that the formula is satisfiable.

Our benchmark sets include in total 371 benchmarks that involve multiple bit-widths, which Baseline does not support. Configuration Pbv solves 178 instances, 20 of which are satisfiable. Configuration Eager solves 110 instances, all of which are unsatisfiable.

Simplifying the TPBV-formula via rewriting as described in Section 4.1 is overall beneficial for both the Eager and the Pbv configurations but has a bigger impact on Eager. Without rewriting, Eager solves 474 fewer instances, while Pbv only loses 72 instances.

Proving the correctness of the invertibility conditions from [28] for arbitrary bit-widths (benchmark set ic) has previously been attempted with two different approaches: (i) the eager TPBV approach described in [30] and (ii) a bit-width independent formalization in Coq [12]. Out of the 81 invertibility conditions proven across our three configurations, 11 were not proven by (i) and (ii). Of these 11, 8 involve multiple bit-widths which neither (i) nor (ii) can handle. The remaining 3 conditions involve operators that are not supported by (ii) (signed inequalities, multiplication and division).

For benchmarks in sets lemmas and icfb, we provide the first bit-width independent verification. The lemmas and conditions in these sets were only proven correct for a range of fixed bit-widths [31, 24]. Configuration Pbv was able to confirm that the incorrect condition is indeed incorrect. However, it was unable to prove the corrected condition within the given time limit.

6 Conclusion and Further Research

We have presented a new theory of parametric bit-vectors TPBV and proposed a dedicated, lazy procedure for solving TPBV-formulas. We have shown experimentally that our techniques are a significant improvement over previous techniques in a wide range of benchmarks.

In future work, we plan to explore proof production for parametric bit-vectors, based on the algorithms presented in this paper. This will enable the integration of the proposed solver into proof assistants like Coq [11], Lean [22] or Isabelle/HOL [32], in order to increase automation in these tools for proofs involving parametric bit-vectors.

For our evaluation, we compiled sets of benchmarks for various challenging applications. These benchmarks are, however, relatively small in terms of formula size. It would be interesting to evaluate the scalability of our approach with respect to formula size. However, obtaining appropriate benchmarks for this purpose is currently challenging.222For example, parameterizing bit-vector benchmarks from SMT-LIB (which are exclusively over fixed-size bit-vectors) while preserving their semantics is not straightforward. Generating and experimenting with such benchmarks is left for future work.

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Appendix A Rewrite Rules of the Parametric Bit-Vector Rewriter 𝓡𝓦𝓑

The following table lists the rewrite rules implemented in our rewriter 𝒲. We denote with kx the bitwidth of x, use a lexicographic ordering <lex between terms, and normalize commutative operations (+, &, etc.) according to this ordering. For example, if t1<lext2, then t1+t2 is rewritten to itself and t2+t1 is rewritten to t1+t2.

Rule Name Term Rewritten Term
bv-concat-extract-merge (concat (extract k (+ j 1) s) (extract j i s) ) (extract k i s)
bv-extract-extract (extract l k (extract j i x)) (extract (+ i l) (+ i k) x)
bv-extract-whole (extract kx 0 x) x
bv-add-zero (bvadd x 0) x
bv-reverse-extract-and (bvand (extract j i x) (extract j i y)) (extract j i (bvand x y))
bv-xor-simplify-2 (bvxor x (bvnot x)) (bvnot 0)
bv-or-zero (bvor x (int_to_pbv kx 0)) x
bv-mul-one (bvmul x (int_to_pbv kx 1)) x
bv-mul-zero (bvmul x (int_to_pbv kx 0)) (int_to_pbv kx 0)
bv-zero-extend-eliminate (zero-extend 0 x) x
bv-sign-extend-eliminate (sign-extend 0 x) x
bv-not-neq (= x (bvnot x)) false
bv-neg-sub (bvneg (bvsub x y)) (bvsub y x)
bv-neg-idemp (bvneg (bvneg x)) x
bv-ugt-eliminate (bvugt x y) (bvult y x)
bv-uge-eliminate (bvuge x y) (bvule y x)
bv-sgt-eliminate (bvsgt x y) (bvslt y x)
bv-sge-eliminate (bvsge x y) (bvsle y x)
bv-shl-by-const-0 (bvshl x (int_to_pbv kx 0)) x
bv-shl-by-const-2 (bvshl x (int_to_pbv kx kx)) (int_to_pbv kx 0)
bv-lshr-by-const-0 (bvlshr x (int_to_pbv kx 0)) x
bv-lshr-by-const-2 (bvlshr x (int_to_pbv kx kx)) (int_to_pbv kx 0)
bv-ashr-by-const-0 (bvashr x (int_to_pbv kx 0)) x
bv-bitwise-idemp-2 (bvor x x) x
bv-or-one (bvor x (bvnot x)) (bvnot (int_to_pbv kx 0))
bv-xor-duplicate (bvxor x x) (int_to_pbv kx 0)
bv-xor-zero (bvxor x (int_to_pbv kx 0)) x
bv-bitwise-not-or (bvor x (bvnot x)) (bvnot (int_to_pbv kx 0))
bv-xor-not (bvxor (bvnot x) (bvnot y)) (bvxor x y)
bv-not-idemp (bvnot (bvnot x)) x
bv-ult-zero-1 (bvult (int_to_pbv kx 0) x) (not (= x (int_to_pbv kx 0)))
bv-ult-zero-2 (bvult x (int_to_pbv kx 0)) false
bv-ult-self (bvult x x) false
bv-lt-self (bvslt x x) false
bv-ule-self (bvule x x) true
bv-ule-zero (bvule x (int_to_pbv kx 0)) (= x (int_to_pbv kx 0))
bv-zero-ule (bvule (int_to_pbv kx 0) x) true
bv-sle-self (bvsle x x) true
bv-ule-max (bvule x (bvnot x)) true
bv-udiv-zero (bvudiv x (int_to_pbv kx 0)) (bvnot (int_to_pbv kx 0))
bv-udiv-one (bvudiv x (int_to_pbv kx 1)) x
bv-urem-one (bvurem x (int_to_pbv kx 1)) (int_to_pbv kx 0)
bv-urem-self (bvurem x x) (int_to_pbv kx 0)
bv-shl-zero (bvshl (int_to_pbv kx 0) x) (int_to_pbv kx 0)
bv-lshr-zero (bvlshr (int_to_pbv kx 0) x) (int_to_pbv kx 0)
bv-ashr-zero (bvashr (int_to_pbv kx 0) x) (int_to_pbv kx 0)
bv-ult-one (bvult x (int_to_pbv kx 1)) (= x (int_to_pbv kx 0))

Appendix B More Detailed Evaluation

In addition to the experimental evaluation presented above, we have performed an in-depth ablation study of the various features listed in Table 5. In this section, we describe the results for 14 configurations we evaluated in addition to the three described in Table 5. These additional configurations are defined as described in Tables 7 and 8.

Configuration or-e is obtained from Baseline by turning on the elimination of , and similarly for xor-e. The right-most 6 configurations of Table 8 differ by turning on or off the bit-vector rewriter 𝒲, as well as the arithmetic optimizations that eliminate mod operators. In particular, Eager - is obtained from Eager by turning both of these off.

The results of the additional configurations are shown in Tables 9 and 10. Table 9 focuses on configurations that are based on Baseline. Note that the elimination of mod in >> (configuration sh-m-e) has a greater effect than the elimination of and , since our benchmarks include more occurrences of >>. Table 10 includes configurations that evaluate the effect of the bit-vector rewriter 𝒲. Overall, enabling the rewriter improves performance, especially for the eager configurations.

Table 7: Intermediate configurations with T1=T𝐼𝐴(pow2,&,,).
Feature or-e xor-e sh-m-e all-e pow2++ piand++
Target Theory T1
Multiple Bit-widths
Lazy pow2
Lazy &
-elimination
-elimination
>> without mod
New lemmas for &
New lemmas for pow2
No redundant axioms
𝒲
mod-reduction
Table 8: Intermediate configurations. T3=T𝐼𝐴(pow2,&), that is, pow2 has a fixed interpretation, while & is freely interpreted. T4=T𝐼𝐴(pow2,&), that is, & has a fixed interpretation, while pow2 is freely interpreted. T5=T𝐼𝐴(pow2,&). T2=T𝐼𝐴(pow2,&).
Feature pow2-l piand-l Eager - Eager Eager- Pbv Pbv - Pbv-
Target Theory T3 T4 T5 T5 T5 T2 T2 T2
Multiple Bit-widths
Lazy pow2
Lazy &
-elimination
-elimination
>> without mod
New lemmas for &
New lemmas for pow2
No redundant axioms
𝒲
mod-reduction
Table 9: Overall number of solved benchmarks for each configuration. VBS corresponds to the virtual best solver over all three configurations.
Benchmarks # or-e xor-e sh-m-e all-e pow2++ piand++ VBS
alive 200 71 71 71 71 71 71 72
ic 180 44 44 48 49 43 43 50
rewrite 2006 692 653 724 758 669 633 809
syrew 1500 561 556 604 603 570 551 625
lemmas 70 12 12 13 13 12 12 13
icfb 46 1 1 1 1 1 1 1
mut 9441 692 663 774 794 669 634 843
total 13443 2071 2000 2235 2289 2033 1945 2413
sat 0 0 0 0 0 0 0
unsat 2071 2000 2235 2289 2033 1955 2413

Table 10: Overall number of solved benchmarks for each configuration. VBS corresponds to the virtual best solver over all three configurations.
Benchmarks # pow2-l piand-l Eager - Eager Eager- Pbv Pbv - Pbv- VBS
alive 200 63 74 87 95 85 105 97 100 125
ic 180 55 45 58 59 59 75 75 77 83
rewrite 2006 681 797 732 925 1068 1296 1148 1189 1381
syrew 1500 580 593 608 721 606 911 796 798 956
lemmas 70 17 13 14 14 14 23 23 23 25
icfb 46 1 1 9 9 9 11 11 12 12
mut 9441 732 733 885 902 1088 4832 4840 4881 5138
total 13443 2129 2256 2393 2725 2929 7253 6990 7080 7720
sat 0 0 0 0 0 3652 3657 3651 3841
unsat 2129 2256 2393 2725 2929 3601 3333 3429 3879