Abstract 1 Introduction 2 Preliminaries 3 The probabilistic rank of 𝟑-𝗣𝗧𝗙s 4 #SAT algorithms for 𝗔𝗖𝗖𝟎𝟑-𝗣𝗧𝗙 circuits References

#SAT-Algorithms for Classes of Threshold Circuits Based on Probabilistic Rank

Nutan Limaye ORCID IT University of Copenhagen, Denmark Adarsh Srinivasan ORCID Rutgers University, Piscataway, NJ, USA Srikanth Srinivasan ORCID University of Copenhagen, Denmark
Abstract

There is a large body of work that shows how to leverage lower bound techniques for circuit classes to obtain satisfiability algorithms that run in better than brute-force time [24, 38]. For circuits with threshold gates, there are several such algorithms based on either

  • Probabilistic Representations by low-degree polynomials, which allow for the use of fast polynomial evaluation algorithms, or

  • Low rank, which allows for an efficient reduction to rectangular matrix multiplication.

In this paper, we use a related notion of probabilistic rank to obtain satisfiability algorithms for circuit classes contained in 𝖠𝖢𝖢03-𝖯𝖳𝖥, i.e. constant-depth circuits with modular counting gates and a single layer of degree-3 polynomial threshold functions.

Even for the special case of a single 3-𝖯𝖳𝖥, it is not clear how to use either of the above two strategies to get a non-trivial satisfiability algorithm. The best known algorithm in this case previously was based on memoization and yields worse guarantees than our algorithm.

Keywords and phrases:
probabilistic polynomials, probabilistic rank, circuit satisfiability, circuit lower bounds, polynomial method, threshold circuits
Funding:
Nutan Limaye: Received funding from the Independent Research Fund Denmark (grant agreement No. 10.46540/3103-00116B) and is also supported by the Basic Algorithms Research Copenhagen (BARC), funded by VILLUM Foundation Grants 16582 and 54451, and Digital Research Centre Denmark, project P40.
Adarsh Srinivasan: Supported by the National Science Foundation under Grants CCF-2313372 and CCF-2443697. Part of this work was done during a visit to ITU Copenhagen and BARC funded by Basic Algorithms Research Copenhagen(BARC), supported by VILLUM Foundation Grants 16582 and 54451, and while at INSAIT, Sofia University “St. Kliment Ohridski”, Bulgaria. This work was partially funded from the Ministry of Education and Science of Bulgaria (support for INSAIT, part of the Bulgarian National Roadmap for Research Infrastructure).
Srikanth Srinivasan: Funded by the European Research Council (ERC) under grant agreement no. 101125652 (ALBA).
Copyright and License:
[Uncaptioned image] © Nutan Limaye, Adarsh Srinivasan, and Srikanth Srinivasan; licensed under Creative Commons License CC-BY 4.0
2012 ACM Subject Classification:
Theory of computation Computational complexity and cryptography
Editors:
Paweł Gawrychowski, Filip Mazowiecki, and Michał Skrzypczak

1 Introduction

Satisfiability algorithms and lower bounds

Given a family of circuits 𝒞, a fundamental algorithmic question one can ask about it is the satisfiability question: does a given C𝒞 have a satisfying assignment? This being a canonical 𝖭𝖯-complete problem even for very simple 𝒞, it is hard to imagine a polynomial-time algorithm for this problem. However, it is still reasonable to try to obtain some speed-up over brute-force search. Typically, and also in this paper, we aim for running times of 2ns where n denotes the number of variables and s is the “savings” over brute-force search.111The trivial algorithm evaluates the circuit on every input, which takes time at least 2n.

A long line of work has leveraged structural understanding from complexity-theoretic research on circuit lower bounds to devise satisfiability algorithms for various families of circuits. For example, these ideas have led to approaches to satisfiability algorithms for constant-depth circuit classes [24, 17, 37, 25], Boolean formulas [29, 30] and Threshold circuits of various kinds [34, 12, 18, 9, 7].

A profound result of Williams [36, 38] also makes a connection in the opposite direction, by showing that satisfiability algorithms with savings ω(logn) for many “reasonable” circuit classes implies lower bounds for these classes.222i.e. a superpolynomial improvement over brute-force This gives even more impetus to studying the satisfiability problem in this regime.

Lower bound techniques in satisfiability algorithms

There are a handful of techniques from complexity-theoretic investigations that are useful in devising satisfiability algorithms. These include

  • Memoization: In the setting of lower bounds, this idea goes back to the work of Nechiporuk [22] who used it to show quadratic Boolean formula lower bounds. This idea can also be used to obtain satisfiability algorithms in some settings (see e.g. [28, 7]). To apply this technique to a circuit class 𝒞, one must be able to prove a strong upper bound on the number of functions in 𝒞 of a given size. Unfortunately, in most algorithmic settings (e.g. CNF formulas of unbounded width), one cannot get a strong enough upper bound of this form to get much out of this technique.

  • Restriction-based techniques: A popular family of techniques used to devise satisfiability algorithms is the idea of restricting a subset of the variables (i.e. setting them to Boolean assignments) in a way that simplifies the underlying circuit and allows us to circumvent having to try all settings of the other variables. This leads to DPLL-style algorithms for SAT and their extensions to 𝖠𝖢0 circuits [17] and Boolean formulas [29] based on results such as the Håstad Switching Lemma [15, 16]. Unfortunately, these arguments do not extend to circuit classes where the gate set contains gates other than the DeMorgan basis (e.g. XOR gates or Majority gates that count the number of 1s) unless severe size restrictions are placed on the circuits [12, 18].

This brings us to the topic of this paper, where we study circuits with threshold gates. For an integer d, a Polynomial Threshold Function (PTF) of degree d is defined to be a Boolean function f:{0,1}n{0,1} such that there exists a multilinear polynomial P of degree d with integer coefficients such that for each x{0,1}n, f(x)=1 if and only if P(x)>0. We denote by d-𝖯𝖳𝖥 the class of polynomial threshold functions of degree d. The special case d=1 is denoted 𝖫𝖳𝖥.

Even the problem of checking if a given f2-𝖯𝖳𝖥 is satisfiable is an 𝖭𝖯-complete problem.333Here, the input is given as a polynomial P with integer coefficients that represents f in the sense described above. Further, the problem for d-𝖯𝖳𝖥 is a considerable generalization of the problem of optimizing a MAX-d-CSP over Boolean variables. While we know algorithms for MAX-2-CSP with savings Ω(n) [35], obtaining such a result even in the case of 3-CSPs remains an elusive problem. For the best known result for d4 see the work of Alman, Chan, and Williams [3].

We will consider algorithms for classes of polynomial-sized circuits using PTF gates (and also other counting gates). In such situations, neither memoization nor restriction-based techniques seem to be useful in devising satisfiability algorithms, except in very special cases (as we will explain below). However, there are some known algorithms that work for such circuit classes. Mostly, they exploit the following ideas.

  • Polynomial representations: This is a powerful circuit-analysis technique going back to a foundational circuit lower bound due to Razborov [26, 32] and follow-up results of Yao [39] and Beigel and Tarui [8] which were aimed towards proving bounds for constant-depth circuits with AND, OR, NOT and modular counting gates. Here, it is shown that small circuits from this class can be represented by (sometimes randomized) polynomials. By making this technique algorithmic and using fast polynomial evaluation algorithms, Williams [38] devised the first satisfiability algorithms for these circuits with non-trivial savings, leading also to his breakthrough circuit lower bound for the class 𝖠𝖢𝖢0.

  • Rank techniques: Another powerful idea is to reduce the problem of checking satisfiability to computing the entries of a low-rank matrix. Typically, this is done by splitting the n variables into two subsets of size n/2 and showing that the 2n/2×2n/2-sized matrix obtained by evaluating the given input circuit C on all pairs of inputs (x,y){0,1}n/2×{0,1}n/2 is (a simple function of) a low-rank matrix. By using fast algorithms for rectangular matrix multiplication [14, 34], this leads to satisfiability algorithms for classes such as 𝖠𝖢𝖢0𝖫𝖳𝖥.

In this work, we show how to extend these ideas to polynomial threshold functions of degree up to 3 and generalizations thereof. It is unclear if either of the above techniques can be used directly to obtain non-trivial savings in this setting.444It should be noted that a PTF of degree d has a low-degree polynomial (sign) representation by definition. However, this alone is not enough to devise a satisfiability algorithm. We also need a low-degree polynomial representation for a disjunction of superpolynomially many PTFs, and whether this stronger property holds is unclear. In fact, it seems unlikely [31]. More precisely, we obtain the following results. See Section 2 for definitions.

Theorem 1 (Informal).

We have the following satisfiability algorithms.

  • For any fixed prime p, a deterministic algorithm for counting the number of satisfying assignments of a given polynomial-sized 𝖠𝖢0[𝖬𝖮𝖣p]3-𝖯𝖳𝖥 circuit with savings Ω~(n) over brute-force search.

  • A deterministic algorithm for counting the number of satisfying assignments of a given polynomial-sized 𝖠𝖢𝖢03-𝖯𝖳𝖥 circuit with savings Ω(nε) where ε depends on the depth of the circuit.

Even in the case of a single 3-𝖯𝖳𝖥, the running time of our algorithm beats the best-known previous algorithm of [7], which was based on memoization and yielded savings of Ω~(n1/3). Moreover, as mentioned above, the technique of memoization does not seem to be useful even for simple extensions of this class to, say, conjunctions of polynomially many 3-PTFs.

As a consequence of our theorem and the algorithmic method of Williams, extended by Murray and Williams [38, 21], we also derive the first lower bound for the circuit class 𝖠𝖢𝖢03-𝖯𝖳𝖥.

Main idea

The main idea behind our algorithm is similar to the idea used in the work of Alman, Chan and Williams [3] for MAX-4-CSPs. Specifically, we combine the two techniques mentioned above into a probabilistic rank upper bound for the classes of circuits we consider. For simplicity, consider the case when the input is a polynomial P(z1,,zn) of degree 3 representing a 3-PTF f and we want to know if f is satisfiable.

As above, we split the n Boolean variables of P into two disjoint sets A={1,,n/2} and B={n/2+1,,n} of size n/2 and consider the matrix Mf of size 2n/2×2n/2 where the rows and columns are labelled by settings to variables indexed by A and B respectively and

Mf(x,y)=f(x,y)

for each x,y{0,1}n/2. Now, while we cannot argue that Mf is low-rank, we can argue that there is a low-rank (roughly exp(O~(n)2n/2) random matrix 𝐌 that agrees with Mf in each entry w.h.p. To do this, we write

P(x1,,xn/2,y1,,yn/2)=i=1n/2xiQi(y1,,yn/2)+j=1n/2yjRj(x1,,xn/2)+Q(y)+R(x) (1)

by noting that each monomial in P must have degree at most 1 either in the variables indexed by A or by B. Partitioning the monomials that have variables in both parts according to choice of this “special” variable gives the decomposition above (Q and R contain the monomials that contain variables indexed by only one of B or A respectively). This type of decomposition is exactly like that obtained by [3]. From this point on our proof outline is also quite similar. The main place where we differ is that we need to handle weights which are not necessarily polynomially bounded.

We continue as follows. Note that f(x,y) can be written as the sign of the above expression. To express Mf as a low-rank matrix (probabilistically), we use constructions of probabilistic polynomials (see definition in Section 2) for the Majority function555This idea works when the coefficients of the underlying polynomial P are all polynomially small. Our algorithm can also handle coefficients that are exponentially large. In this case, we need some additional circuitry to simulate the sum efficiently. This can be converted to a low-degree polynomial using the construction of Razborov [26, 25]. and variants [6, 3] which allows us to write the above as a random polynomial of degree at most O~(n) over the bits of the numbers

x1,,xn/2,R1(x),,Rn/2(x),R(x),y1,,yn/2,Q1(y),,Qn/2(y),Q(y).

Each monomial in the polynomial defines a rank-1 matrix, as it is a product of the form F(x)G(y) for some functions F and G. A polynomial of degree O~(n) thus defines a matrix of rank exp(O~(n)).

To extend the above to (say) 𝖠𝖢𝖢03-𝖯𝖳𝖥, we compose the above construction with standard low-degree polynomial representations of the class 𝖠𝖢𝖢0 [2, 8].

This structural result shows that the family of degree-3 PTFs has low probabilistic rank. This may be of independent interest. Alman and Williams [5] proved such a result for the inner product function, resulting in improved bounds on the rigidity of the Hadamard matrix. Follow-up results have used this idea to give better circuits for computing the Walsh-Hadamard transform [4].

For the satisfiability algorithm, we need to combine this idea with the standard “blow-up trick” of Williams. Returning to the case of a single 3-PTF f(z1,,zn), we will apply the above idea to

g(z1,,zn)=a{0,1}f(z1,,zn,a1,,a).

(Note that g is satisfiable if and only if f is satisfiable.) For suitably small (roughly n), we will apply the above idea to g and show that the analogous matrix Mg has low-rank. By using Coppersmith’s rectangular matrix multiplication algorithm [14, 34], it follows that Mg can be computed in time approximately 2n, leading to savings for our algorithm.

Finally, to count the number of satisfying assignments, we replace the OR above by a sum and use similar ideas (as in [34, 25]).

 Remark 2.

The algorithm for MAX-d-CSP (for the dense case) by [3] is closely related to our algorithm. They are able to make it work for d=4, whereas, we only obtain algorithms for 3-PTF. The main bottleneck seems to be that we are dealing with arbitrary weights, whereas they work with polynomially bounded weights. It is unclear how we can make their ideas work even for a single 4-PTF with arbitrary weights.

Another reason our result does not work for d-PTFs for d4 is that the analogous decomposition to (1) yields a decomposition with mn2 terms, and the probabilistic degree of the Majority function on m variables is Ω(m) [26]. Thus, we only get a polynomial of degree Ω(n), which does not yield a suitably non-trivial bound on the probabilistic rank of these PTFs. It is an interesting open problem to see if any non-trivial upper bounds can be obtained for the probabilistic rank of PTFs of larger degree.

Related work

Over the past decade, there have been many works studying satisfiability algorithms for circuits using threshold gates and modular counting gates.

In the setting of 𝖠𝖢𝖢0, the class of constant-depth circuits using AND, OR, NOT and modular counting gates, the first non-trivial satisfiability algorithms were given by Williams [38] followed by improvements in [34], which also yields algorithms for the class 𝖠𝖢𝖢0𝖫𝖳𝖥. Further extensions have been obtained by works of [3, 11] but neither of these works allow us to replace the LTF gates by PTFs of higher degree.

For a single d-𝖯𝖳𝖥, the best known algorithms use the memoization technique and have savings Ω~(n1/d). [27, 7] This technique is grounded in the fact that the number of degree-d PTFs on n variables is 2O(nd+1) [13], and this does not extend even to simple combinations of PTFs, such as conjunctions of polynomially many PTFs (or even LTFs).666For example, it is easy to show that the number of distinct functions that can be written as a conjunction of s LTFs is always at least 2s as long as n>logs.

There are also restriction-based satisfiability algorithms for circuits made up of LTF and, more generally, PTF gates [12, 18]. Unfortunately, though, these algorithms only work when the size of the circuits (defined in terms of the number of wires) is slightly superlinear in the number of variables.

Paper organization

In Section 3, we upper bound the probabilistic rank of 3-𝖯𝖳𝖥s (Lemma 14) and present a deterministic #SAT algorithm for 𝖠𝖢0[𝖬𝖮𝖣p]3-𝖯𝖳𝖥 circuits (Theorem 17). In Section 4, we present a #SAT algorithm for 𝖠𝖢𝖢03-𝖯𝖳𝖥 circuits (Theorem 20).

2 Preliminaries

Computational model and asymptotic notation

All our algorithms can be implemented in the standard RAM model. The notations poly(n),polylog(n) are used to denote arbitrary, but fixed polynomial and polylogarithmic factors in n respectively. We use the O() and O~() notation to suppress polynomial and logarithmic factors respectively.

The bit complexity of representing 𝗣𝗧𝗙’s

A polynomial threshold function can be defined using multiple polynomials. Hence, the number of bits needed to represent a 𝖯𝖳𝖥 depends on the bit complexity of the polynomial used to define it.

Definition 3 (Bit complexity of a polynomial).

Given a multilinear polynomial P(x1,x2,,xn)=S[n]cSjSxj, the bit complexity of P is defined to be w(P)=log(S[n]|cS|).

It is known that any d-𝖯𝖳𝖥 can be represented using a polynomial with bit complexity upper bounded by O(ndlogn) [20]. However, given an arbitrary d-𝖯𝖳𝖥, it is not clear how to efficiently obtain such a low weight representation. Nevertheless, our algorithms in Section 3 can handle 𝖯𝖳𝖥’s represented by polynomials with bit complexity up to 2nδ, for some fixed δ>0. For the purpose of proving lower bounds, we can always assume that the bit complexity of d-𝖯𝖳𝖥 functions is upper bounded by O(ndlogn).

Boolean circuits

We use the standard definitions for boolean circuits and circuit classes. We refer the reader to [33] for more details. The size of a circuit is defined to be the number of wires and its depth is defined to be the total number of layers. The circuit class 𝖠𝖢0 consists of constant depth circuits with 𝖠𝖭𝖣,𝖮𝖱,𝖭𝖮𝖳 gates of unbounded fan-in. For any m, a 𝖬𝖮𝖣m gate with fan-in t outputs 1 if the sum (over ) of its inputs is divisible by m and outputs 0 otherwise. For any prime p, the class 𝖠𝖢0[𝖬𝖮𝖣p] consists of circuits with 𝖠𝖭𝖣,𝖮𝖱,𝖭𝖮𝖳 and 𝖬𝖮𝖣p gates with unbounded fan-in. The class 𝖠𝖢𝖢0 is defined as circuits of constant depth consisting of 𝖠𝖭𝖣,𝖮𝖱,𝖭𝖮𝖳 and 𝖬𝖮𝖣m gates of unbounded fan-in, for any fixed composite number m.
We define the following class of circuits, which can efficiently represent 𝖠𝖢𝖢0 circuits [1, 2, 8].

Definition 4 (Symmetric functions and 𝖲𝖸𝖬+ circuits).

A boolean function f:{0,1}n{0,1}n is called a symmetric function if there exists a function F:[n]{0,1} such that f(x1,,xn)=F(i=1nxi). A 𝖲𝖸𝖬+ circuit is a depth two boolean circuit with an output gate that computes any symmetric function, and 𝖠𝖭𝖣 gates at the second layer.

We also use modulus amplifying polynomials in our algorithms for 𝖠𝖢𝖢03-𝖯𝖳𝖥 satisfiability.

Definition 5 (Beigel-Tarui modulus amplifying polynomials [8]).

Let p be any prime. For any t, the t-th Beigel Tarui modulus amplifying polynomial is defined as

Ft(z)=(1)t(z1)t(i=0t1(t+i1i)zi)+1.

This polynomial has the property that for all z0,p2, Ft(z)0modpt if z0modp and Ft(z)1modpt if z1modp.

Probabilistic matrices and polynomials

We review some facts on probabilistic matrices and probabilistic polynomials.

Definition 6 (Probabilistic Polynomial).

Let 𝔽 be a field. A probabilistic polynomial over n variables is a distribution of polynomials from 𝔽[x1,x2,,xn]. An ε-error probabilistic polynomial for a Boolean function f:{0,1}n{0,1} is a probabilistic polynomial 𝐏 such that, for every z{0,1}n, PrP𝐏[P(z)=f(z)]1ε. A probabilistic polynomial 𝐏 is said to have degree D if PrP𝐏[deg(P)D]=1.

To derandomize algorithms that use probabilistic polynomials, we will need to design probabilistic polynomials that can be sampled using less randomness. To be precise, we say that a probabilistic polynomial 𝐏 can be sampled in time T(n) using r(n) bits of randomness if there exists a deterministic algorithm 𝒜 that takes as input a string σ{0,1}r(n) and in time T(n) outputs polynomials, such that for each polynomial P, Prσ{0,1}r(n)[𝒜(σ)=P]=𝐏(P). We will also need to reduce the error of a probabilistic polynomial to any arbitrary ε>0.

Lemma 7 (Randomness efficient error reduction for probabilistic polynomials).

Let f be any boolean function on n variables with an 1/3-error probabilistic polynomial of degree D that can be sampled using r bits of randomness in time T(n). Then, for any ε>0 there exists a probabilistic polynomial 𝐐 for f with error ε, and degree O(Dlog(1/ε)). Furthermore, 𝐐 is of the form 𝖬𝖠𝖩(𝐏𝟏,,𝐏), where =O(log(1/ε)) 𝐏𝟏,,𝐏 are probabilistic polynomials of degree D, and there exists an algorithm that uses O(r+log(1/ε)) bits of randomness and outputs 𝐏𝟏,,𝐏 as sums of monomials in time O(T(n)).

Proof.

We refer the reader to the proof of [25, Lemma 16].

The notion of probabilistic matrices and probabilistic rank generalize the notion of probabilistic polynomials and probabilistic degree.

Definition 8 (Probabilistic matrix [5]).

Let R be any ring. Consider any matrix MRN×N. A probabilistic matrix for M with error ε is a distribution over N×N matrices in RN×N such that for each i,j[N]2, PrM[M[i,j]=M[i,j]]1ε. A probabilistic matrix has rank r if every matrix sampled from has rank at most r. A matrix M has ε-probabilistic rank r if there exists a probabilistic matrix for M with error ε and rank r.

Fast rectangular matrix multiplication

All our satisfiability algorithms rely on the fact that we can rapidly multiply rectangular matrices using Coppersmith’s algorithm.

Lemma 9 (Coppersmith’s algorithm [14, 34]).

For sufficiently large N and α0.172 and any field 𝔽 with 2polylog(N) elements, there exists an algorithm that takes matrices A𝔽N×Nα,B𝔽Nα×N as inputs and outputs the matrix AB in time N2polylog(N)

We refer the reader to the appendix of [34] for a proof.

3 The probabilistic rank of 𝟑-𝗣𝗧𝗙s

We start with recalling that there exist probabilistic polynomials for 𝖠𝖢0 circuits with degree polylogarithmic in the size of the circuit.

Lemma 10 (Randomness efficient probabilistic polynomials for 𝖠𝖢0 [25]).

Let p be any prime. Any 𝖠𝖢0[𝖬𝖮𝖣p] circuit of depth d and size s on n variables has an ε-error probabilistic polynomial 𝐏 over the field 𝔽p of degree O((logs)d1log(1/ε)), and a polynomial can be sampled from the distribution in time nO(logs)d1log(1/ε) and using O(log(s)+log(1/ε)) random bits.

Lemma 11.

There exists a probabilistic polynomial for any symmetric boolean function of error 1/3 and degree d=O(nlog(n)). A polynomial can be sampled from the distribution in time O((nd)poly(n)) using O(log2(n)) random bits.

Proof.

Let S[n] be the set of all k[n] such that f(x)=1 if i=1nxi=k. Hence, f(x)=kS(i=1nxi=k). The predicate (i=1nxi=k) can be computed by a 𝖠𝖭𝖣2𝖬𝖠𝖩 circuit with 𝖬𝖠𝖩 gates with O(n) fan-in. Now, 𝖬𝖠𝖩 has a 1/3-error probabilistic polynomial over any field of degree O(n), and a polynomial can be sampled from the probabilistic polynomial using O(log2n) random bits [3]. The 𝖠𝖭𝖣2 gates can be converted into polynomials of degree two trivially. Hence, using Lemma 7, we can sample a probabilistic polynomial of error ε for the predicate (i=1nxi=k) of degree nlog(1/ε) using O(log2(n)+log(1/ε)) random bits. Finally, we can convert the top 𝖮𝖱 gate into a probabilistic polynomial of constant degree and error 1/10 using O(logn) random bits (Lemma 10). Setting ε=110n for the 𝖬𝖠𝖩 gates and composing these polynomials, we get a probabilistic polynomial for the symmetric function of degree O(nlog(n)) using O(log2n) random bits and error 1/3.

Lemma 12.

There exists an 𝖠𝖢0𝖲𝖸𝖬n circuit with poly(n,M) gates that takes as input n integers of M bits each and outputs their sum.

Proof.

Suppose the M bit numbers are A1,A2,,An, where Ai=Ai,M1Ai,M2Ai,0, with Ai,j{0,1}. Let =logn. Let B=B+M1B+M2B0=i=1nAi. For each j=1,2,,M, let yj=yj,1yj,2yj,0=i=1nAi,j. There exist functions f0,f1,f1:[n]{0,1} such that yj,k=fk(i=1nAi,j) for each k=0,2,,1. Then, we can rewrite the sum B as follows.

B=j=0M12ji=1nAi,j=j=0M12jyj =j=0M12j(k=012kfk(i=1nAi,j))
=j=0M1k=012j+kfk(i=1nAi,j).

Switching the order of the summation, this is equal to k=012kj=0M12jfk(i=1nAi,j). For each k=0,2,,1 and j=0,1,,M1, the function fk(i=1nAi,j) can be implemented using a single 𝖲𝖸𝖬 gate with fan-in n. Hence, the numbers Ck=2kj=0M12jfk(i=1nAi,j) can be computed in parallel, for each k=0,1,,1 as bit strings of length =log(n) using a layer of M 𝖲𝖸𝖬 gates of fan-in n. What remains is to compute B=k=01Ck. It is known that addition of logN numbers with N bits each can be implemented using constant depth circuits of size poly(N) [33]. We can use these circuits with N=M+n to prove the lemma.

 Remark 13.

A very similar 𝖠𝖢0𝖬𝖠𝖩-circuit for this problem was first constructed in [19]. However, their construction yields 𝖬𝖠𝖩 gates of fan-in n2. The results in this section require circuits with 𝖬𝖠𝖩 gates with fan-in at most n.

Lemma 14.

Let p be any prime and F:{0,1}n{0,1} be a 3-𝖯𝖳𝖥 defined by a polynomial P[z1,z2,,zn] and bit complexity upper bounded by M. Then there exist functions f,g:{0,1}n/2{0,1}n/2, with n=O(nM) and a probabilistic polynomial 𝐐𝔽p[x1,,xn] of degree npolylog(n,M), such that for each x,y{0,1}n/2,

PrQ𝐐[Q(f(x),g(y))=F(x,y)]2/3.

Given x,y, f(x) and g(y) can be computed in time poly(n,M) and a polynomial can be sampled from 𝐐 using O(logM+log2n) random bits in time 2npolylog(n,M).

 Remark 15.

This implies that there exists an absolute constant δ>0 such that 3-𝖯𝖳𝖥s defined using polynomials of bit complexity upper bounded by 2nδ have probabilistic degree o(n). In several situations, it may also be reasonable to assume that M=poly(n), as noted in Section 2.

Proof.

Note that any cubic polynomial P(x,y) can be decomposed in the following fashion.

P(x,y)=j=1n/2xjQj(y)+j=1n/2yjRj(x)+Q~(y)+R~(x),

for quadratic polynomials Qj,Rj,Q~,R~. We can now define f(x) and g(y) to be the bits of the integers Rj(x),R~(x) and Qj(y),Q~(y) (with an extra bit to store the sign) for each j[n/2] respectively. The number of bits needed to express f(x) and g(y) is upper bounded by O(log(R~(x))+j=1n/2log(Rj(x))) and O(log(R~(y))+j=1n/2log(Qj(y))) respectively. By the definition of bit-complexity of a polynomial, the values of Rj(x),R~j(x),Qj(y),Q~j(y) are upper bounded by 2w(P) and hence by 2M for each j[n/2],x{0,1}n/2, which means that f(x) and g(y) are bit strings of length O(nM).

Converting 𝑭 into a 𝐩𝐨𝐥𝐲(𝒏,𝑴) sized 𝗔𝗖𝟎[]𝗦𝗬𝗠𝒏𝗔𝗡𝗗𝟐 circuit.

We can define a circuit C, which is very similar to the circuit described in the proof of [34, Theorem 1.4] Let 𝖲𝖴𝖬n,M denote a circuit that takes as input up to n natural numbers with bit complexity M and outputs their t=O(M+logn) bit sum. Let 𝖫𝖤𝖰t denote a circuit that takes as input two t bit integers a,b and outputs 1 if ab and 0 otherwise. The bottom-most layer of the circuit consists of 𝖠𝖭𝖣 gates with fan-in two. This layer outputs the bits for xjQj(y), yjRj(x). Now, given the bits of the integers xjQj(y),yjRj(x),Q~(y),R~(x) for all j[m/2], we can compute the output of the 3-𝖯𝖳𝖥 using a 𝖫𝖤𝖰t𝖲𝖴𝖬n,M circuit. This can be accomplished by adding up all the negative and positive integers in parallel using two 𝖲𝖴𝖬n,M subcircuits and then comparing the outputs of these two subcircuits using an 𝖫𝖤𝖰t subcircuit. Now, we note that 𝖫𝖤𝖰t has poly(t) sized 𝖠𝖢0 circuit of depth 4 (see [10] and [37, Appendix A] 777this follows from the following fact: LEQ(x,y)=(i=1t(1+xi+yi))i=1t((1+xi)yij=1i1(1+xj+yj)), where LEQ(x,y)=1 if and only if xy.) and 𝖲𝖴𝖬n,M has a 𝖠𝖢0𝖲𝖸𝖬n circuit with poly(n,M) gates by Lemma 12. Hence, C has poly(n,M) gates.

Converting 𝑪 into a probabilistic polynomial.

The next step is to convert C into a probabilistic polynomial 𝐐. Each of the 𝖠𝖭𝖣2 gates at the bottom can be trivially represented by a constant degree polynomial. Next, we convert each symmetric gate into a probabilistic polynomial of error ε=1(nM)c for sufficiently large c and degree O(nlog(1/ε)logn)=O(nlog(M)polylog(n)) and 2O(nlog(M)polylog(n)) monomials using Lemma 11. We can use union bound to show that that the probability that any of the polynomials for the symmetric gates err is upper bounded by 1/10. The remaining part of C is an 𝖠𝖢0 circuit with S=poly(n,M) gates. This can be converted into a probabilistic polynomial of degree polylog(n,M), O(Mlogn) inputs and error 1/10. Hence, 𝐐 has degree npolylog(n,M). We can then use Lemma 7 obtain a probabilistic polynomial with error ε and degree npolylog(n,M)log(1/ε) for any ε>0.

Randomness and time complexity.

The amount of random bits needed for the probabilistic polynomials for the symmetric gates is O(log2(n)+log(M)) (Lemma 11). Because we are using the union bound, we can just reuse the same random bits for all the symmetric gates. The probabilistic polynomials for the 𝖠𝖢0 part of C can be constructed using O(log(S))=O(logM+logn) random bits (Lemma 10). Lemma 14 implies that all 3-𝖯𝖳𝖥 functions have low probabilistic rank.

Corollary 16.

3-𝖯𝖳𝖥 functions over n variables have probabilistic rank 2O~(n).

Proof.

Any 3-𝖯𝖳𝖥 function F:{0,1}n{0,1} can be defined using a cubic polynomial P with poly(n) bit complexity [20]. Hence, we can use Lemma 14 to define probabilistic matrices 𝐀𝔽p2n/2×r,𝐁𝔽pr×2n/2 for r=2O~(n) such that for each x,y{0,1}n/2, PrA𝐀,B𝐁[(AB)x,y=F(x,y)]2/3. We can sample matrices from the distributions 𝐀,𝐁 as follows. We first sample a polynomial Q from the distribution 𝐐 defined in Lemma 14. The columns of A (and the rows of B) are indexed by monomials in Q. Define the entry of A defined by a monomial cSiSxi for a set S[n] and an assignment x{0,1}n/2 to be cSiS{1,,n/2}(f(x))i, and the entry of B defined by the same monomial and an assignment y{0,1}n/2 to be iS{n/2+1,,n}(g(y))i, where (f(x))i and (g(y))i denote the i-th entry of the strings f(x) and g(y) respectively. Hence, (AB)x,y=P(x,y), which is equal to F(x,y) with probability at least 2/3. We use Lemma 14 to obtain a satisfiability algorithm for 3-𝖯𝖳𝖥-SAT, as well as for more expressive complexity classes involving 3-𝖯𝖳𝖥 gates. The following theorem follows directly from combining Lemma 14 with Lemma 10 and derandomization techniques developed in [25] to design a deterministic #SAT algorithm for 𝖠𝖢0[𝖬𝖮𝖣p]3-𝖯𝖳𝖥 circuits.

Theorem 17.

Let p be any prime number. There exists a deterministic algorithm that counts the number of satisfying assignments to 𝖠𝖢0[𝖬𝖮𝖣p]3-𝖯𝖳𝖥 circuits of depth d in time poly(n,M)2nnpolylog(n,M)logd1(s).

 Remark 18.

This algorithm can handle circuits of size up to 2nδ, for some δ that depends on d as well as circuits with 3-𝖯𝖳𝖥s defined by polynomials with weights upper bounded by 2nδ, for the previously defined δ.

Proof.

We start with designing a probabilistic polynomial for C. Let F1,F2,,Fs1 be the 3-𝖯𝖳𝖥 gates in C, for s1s. Using Lemma 14, design probabilistic polynomials 𝐐𝟏,,𝐐𝐬𝟏 with 2nlog(s)polylog(n,M) monomials and functions f1,g1,fs1,gs1, such that PrQi𝐐𝐢[Qi(fi(x),gi(y))=Fi(x,y)]11210s. The polynomials can be sampled using a common set of O(logM+log2n+log(s)) random bits, using Lemma 14 and Lemma 7. We can sample a probabilistic polynomial of error 1/3 for the 𝖠𝖢0 part of C of degree O(logd2s) and O(logs) random bits using Lemma 10. Composing these polynomials and using  Lemma 7 again, we can obtain a probabilistic polynomial 𝐏 with 2npolylog(n,M)logd1slog(1/ε) monomials using O(logM+log2n+logs+log(1/ε)) bits of randomness and functions f,g:{0,1}n/2{0,1}O(nMs) such that PrP𝐏[P(f(x),g(y))=C(x,y)]1ε. Furthermore, 𝐏=𝖬𝖠𝖩(𝐏𝟏,𝐏𝟐,,𝐏), for probabilistic polynomials 𝐏𝟏,𝐏𝟐,,𝐏 with 2npolylog(n,M)logd1s monomials and =O(log(1/ε)).

The satisfiability algorithm now follows from a standard approach to designing circuit satisfiability algorithms, first used by Williams [38] for 𝖠𝖢𝖢0 satisfiability algorithms. Later on, in [25], this algorithm was derandomized and extended to count the number of satisfying assignments. Pick some nn/2, and let m:=nn. For each x,y{0,1}m/2, let G(x,y):=|{z{0,1}n:C(z,x,y)=1}|. For each z{0,1}n, let Cz denote the circuit C, with the first n variables restricted according to the assignment z. By definition,

G(x,y)=z{0,1}nC(z,x,y)=z{0,1}nCz(x,y),

and #SAT(C)=x,y{0,1}m/2G(x,y). Now, for each z{0,1}n, define functions fz,gz and probabilistic polynomials 𝐏z on O(mMs) variables such that PrPz𝐏z[Pz(fz(z),gz(y))=Cz(x,y)]11/210n using Lemma 14. These can be sampled using r=O(logM+log2n+logs+n) common random bits. For each σ{0,1}r, let Pz,σ=𝖬𝖠𝖩(P1z,σ,,Pz,σ) for =O(n) denote the polynomial sampled from 𝐏z using the string σ as the random bits. Hence,

σ{0,1}rPz,σ(f(x),g(y))={2r(11210n) if Cz(x,y)=12r210n if Cz(x,y)=0

Summing over all z{0,1}n,

2r(1129n)G(x,y) σ{0,1}rz{0,1}n(Pz,σ(fz(x),gz(y))modp)
2r(1+129n)G(x,y) (2)

where the sum is over , not 𝔽p.

Fourier coefficients

Letting 𝖬𝖠𝖩 be a function from pp888We just let 𝖬𝖠𝖩 be the standard majority function on z{0,1}, and arbitrarily set it to (say) 0 on all other z𝔽p, we can define coefficients ka for each a𝔽p, such that 𝖬𝖠𝖩(z1,,z)=a𝔽pka(i=1aizimodp). The quantity (i=1aizimodp) is interpreted as a real number. The numbers ka can be computed for each a𝔽p in time 2O() using the FFT algorithm. We refer the reader to [23] for more details. Define the polynomials Paz,σ:=i=1aiPiz,σ, and let Ft denote the t-th Beigel-Tarui modulus amplifying polynomial (Definition 5).

The parameters

Set n=np(logM,logn)logd1s for a suitable polynomial p. Let m:=nn We remind the reader that =An and that r=B(logM+log2n+logs+log(1/ε))=O(logM+log2n+logs+logn) for constants A,B. We choose t=n/log2(p)++r/log2(p)+10. Now, we can present the deterministic algorithm.

  1. 1.

    Calculate the coefficients ka for each a𝔽p for 𝖬𝖠𝖩.

  2. 2.

    For each z{0,1}n,σ{0,1}r,a𝔽p, construct the polynomials Paz,σ as sums of monomials and functions fi,gi, using Lemma 14.

  3. 3.

    For each i{1,2,,2n}, construct as a sum of monomials, the polynomial

    R:=z{0,1}nσ{0,1}ra𝔽pkaFtPaz,σ.
  4. 4.

    For each x,y{0,1}m/2, evaluate R(f(x),g(y)) using Coppersmith’s algorithm.

  5. 5.

    Output (x,y){0,1}m/2×{0,1}m/2[(R(f(x),g(y))modpt)/2r] (where [] denotes the nearest integer function).

Running time

Step 1 takes time 2O()=2O(n), which can be upper bounded (very loosely) by 2n/10poly(n,M,s). Step 2 takes time 2n+r+log2p2nlogd1spolylog(n,M), which can be upper bounded by 2n/10poly(n,M,s) as well. To upper bound the complexity of Step 3, note that R has 2n+r+log2p2tnlogd1spoly(logn,logM) monomials. Choosing the polynomial p appropriately, this can be upper bounded by 20.01n. Hence, we can construct the polynomial for each a,z,σ in time poly(n,M,s)2n/10. Because the number of monomials in R is upper bounded by 20.05m, Step 4 takes 2mpoly(m) time (Lemma 9). Step 5 runs in 2mpoly(m) time as well.

Correctness

From the properties of the modulus amplifying polynomials (Definition 5), Ft(Paz,σ(f(x),g(y)))0modpt if Paz,σ(f(x),g(y))0modp, and Ft(Paz,σ(f(x),g(y)))1modpt if Paz,σ(f(x),g(y))1modp. Because we have chosen t such that pt>p2r2n,

z{0,1}nσ{0,1}r(Pz,σ(f(x),g(y))modp)
=z{0,1}nσ{0,1}r(𝖬𝖠𝖩(P1z,σ(f(x),g(y)),,Pz,σ(f(x),g(y))modp))
z{0,1}nσ{0,1}ra𝔽pka(i=1aiPiz,σ(f(x),g(y))modp)
=z{0,1}nσ{0,1}ra𝔽pka(Paz,σ(f(x),g(y))modp)
z{0,1}nσ{0,1}ra𝔽pka(Ft(Paz,σ(f(x),g(y)))modpt)
=z{0,1}nσ{0,1}ra𝔽pkaFt(Paz,σ(f(x),g(y)))modpt
=R(f(x),g(y))modpt.

Note that all summations above are over unless they are enclosed by brackets. Now, consider the quantity z{0,1}nσ{0,1}r(Pz,σ(f(x),g(y))modp). Using Section 3, R(f(x),g(y))modpt=z{0,1}nσ{0,1}r(Paz,σ(f(x),g(y))modp)[2r(11/29n)G(x,y),2r(1+1/29n)G(x,y)]. Hence, [12r(R(f(x),g(y))modpt)]=G(x,y). Because #SAT(C)=x,yG(x,y), the algorithm indeed outputs #SAT(C).

4 #SAT algorithms for 𝗔𝗖𝗖𝟎𝟑-𝗣𝗧𝗙 circuits

In this section, we show that Lemma 14 an be combined with with well known techniques [1, 2, 38] for simplifying 𝖠𝖢𝖢03-𝖯𝖳𝖥 circuits to design #SAT algorithms.

Notation

We say that a 𝖲𝖸𝖬𝖠𝖢𝖢03-𝖯𝖳𝖥 circuit has parameters (n,s,M) if it has n inputs, s wires, and contains 3-𝖯𝖳𝖥 gates defined by polynomials with bit-complexity upper bounded by M.
We present a better than brute force algorithm to evaluate 𝖲𝖸𝖬𝖠𝖢𝖢03-𝖯𝖳𝖥 circuits on all inputs.

Theorem 19.

There exists an absolute constant δ(0,1) and a function ε:(0,1) such that the following holds. There exists a deterministic algorithm that takes as input a 𝖲𝖸𝖬𝖠𝖢𝖢03-𝖯𝖳𝖥 circuit C with parameters (n,s,M) such that s2nε(d),M2nδ that can enumerate all satisfying assignments to C in time O(2n).

Using the approach developed in [34] for reducing #SAT to rapid evaluation of large circuits of all inputs, we can design a #SAT algorithm for 𝖠𝖢𝖢03-𝖯𝖳𝖥 circuits. We refer the reader to the proof of [34, Theorem 1.2].

Theorem 20.

There exists an absolute constant δ(0,1) and a function ε:(0,1) such that the following holds. There exists a deterministic algorithm that takes as input an 𝖠𝖢𝖢03-𝖯𝖳𝖥 circuit C with parameters (n,s,M) such that s2nε(d),M2nδ that can count the number of satisfying assignments to C in time O(2nnε(d)).

Using [21, Theorem 1.2], we can infer the following circuit lower bound, which is an extension of [21, Theorem 1.3].

Corollary 21.

For every constant k,d,m, there exists e1 and a problem in 𝖭𝖳𝖨𝖬𝖤(2logen) which does not have 𝖠𝖢𝖢03-𝖯𝖳𝖥 circuits with 𝖬𝖮𝖣m gates of depth d and size 2logkn.

The rest of this section is devoted to the proof of Theorem 19. The first step is to convert 𝖲𝖸𝖬𝖠𝖢𝖢03-𝖯𝖳𝖥 circuits into equivalent 𝖲𝖸𝖬+ circuits.

Lemma 22.

There exists a function c: and an absolute constant e such that the following holds. Let C be any 𝖲𝖸𝖬𝖠𝖢𝖢03-𝖯𝖳𝖥 circuit with parameters (n,s,M). Then, there exists a 𝖲𝖸𝖬+ circuit D and functions f,g such that for each x,y{0,1}n/2, C(x,y)=D(f(x),g(y)). The circuit D has size 2O(logc(d)s)+2O(loges2n(lognlogM)e), and there exists a deterministic algorithm that takes C as input and outputs D in time 2O(logc(d)s)+2O(loges2n(lognlogM)e). The functions f and g output strings of length O(nMs) and are computable in time O(spoly(n,M)). The output of the symmetric gate can be computed in time 2O(logc(d)s), given the number of input wires that evaluate to 1.

Proof.

Let g denote the symmetric gate at the top, with fan-in h, and let H:[h]{0,1} be the symmetric function it computes. Let Ci, for i[h] denote the subcircuits of C that feed into the top 𝖲𝖸𝖬 gate.

Step 1: Replace the 𝟑-𝗣𝗧𝗙 gates with probabilistic polynomials.

Suppose that C has s1 3-𝖯𝖳𝖥 gates F1,F2,,Fs1 in the bottom layer, where s1s. Let ε=110hs, and construct probabilistic polynomials 𝐏𝟏,,𝐏𝐬𝟏 with error ε for each of the 3-𝖯𝖳𝖥 gates, with functions f1,f2,,fs1,g1,g2,,gs1 such that for each j[s1], PrP𝐏𝐣[P(fj(x),gj(y))=Fj(x,y)]1110hs using Lemma 14. Note that each polynomial can be represented as an 𝖷𝖮𝖱𝖠𝖭𝖣 circuit, of size at most 2O(nlogspolylog(n,M)). Hence, we can replace the 𝖲𝖸𝖬𝖠𝖢𝖢03-𝖯𝖳𝖥 circuit C with a probabilistic 𝖲𝖸𝖬𝖠𝖢𝖢0𝖠𝖭𝖣 circuit C of size s=2O(nlogspolylog(n,M)), depth d+1 such that for each x,y{0,1}n/2, C(x,y)=C(f1(x),,fs1(x),g1(y),,gs1(y)) with probability at least 9/10.999Technically, this is not an 𝖠𝖢𝖢0 circuit as it contains 𝖬𝖮𝖣m gates as well as 𝖬𝖮𝖣2 gates, but rest of the transformations will work for this circuit as well. The fan-in of the 𝖠𝖭𝖣 gates at the bottom is upper bounded by O(nlogspolylog(n,M)) and the number of 𝖠𝖭𝖣 gates is upper bounded by 2O(nlogspolylog(n,M)). Note that if the wires from the 𝖠𝖭𝖣 gates at the bottom layer to the rest of the 𝖠𝖢𝖢0 circuit are not counted, C has size O(s), and that the polynomials 𝐏𝟏,,𝐏𝐬𝟏 and hence the circuit C can be sampled using O(log2n+logs) random bits.

Step 2: Replace the 𝗦𝗬𝗠𝗔𝗖𝗖𝟎 circuit 𝑪 with a deterministic 𝗦𝗬𝗠+ circuit.

We use the ideas of Allender and Gore [1, 2]. We refer the reader to Williams [38, Appendix A] for more details. Specifically, we will refer to transformations 1,2,3 and 4, as defined by Williams. Here, we just demonstrate where our proof differs from theirs.

Step 2a.

Apply transformation 1 to the circuit C. This transformation only acts on the 𝖠𝖢𝖢0 part of C and leaves the bottom layer of 𝖠𝖭𝖣 gates untouched. The 𝖬𝖮𝖣m gates for composite m are eliminated and replaced by subcircuits with prime modulo gates and 𝖠𝖭𝖣 gates. Further, all the 𝖠𝖭𝖣 and 𝖮𝖱 gates are all replaced by fixed depth circuits with only 𝖠𝖭𝖣 gates with polylog(n) fan-in and 𝖬𝖮𝖣p gates (for some prime number p). All these gates share a common set of polylog(s) probabilistic inputs. Let the new circuit be C′′, and let C1′′,C2′′,,Ch′′ be the subcircuits that feed into the symmetric gate g. The circuit C′′ has size poly(s), without counting the bottom layer. Over the probabilistic inputs as well as the O(log2n+logs) random bits used to sample the probabilistic polynomials, Pr[Ci′′(f1(x),,fs1(x),g1(y),,gs1(y))=Ci(x,y)]110h. This step takes poly(s) time.

Step 2b.

Let r=O(log2n+polylog(s)) denote the number of random bits needed in total to sample C′′. For each σ{0,1}r, let Cσ′′ denote the circuit C′′ sampled using the string σ as the random bits, and let Ci,σ′′ for i[h] denote the corresponding subcircuits that feed into the top 𝖲𝖸𝖬 gate. Now ,suppose that i[h]Ci(x,y)=t. For each x,y{0,1}n/2, 12rσ{0,1}rCi,σ′′(f(x),g(y))[11/(10h),1] if Ci(x,y)=1 and 2rσ{0,1}rCi,σ′′(f(x),g(y))[0,1/(10h)] if Ci(x,y)=0, Hence, 12ri[h]σ{0,1}rCi,σ′′(f(x),g(y))[t1/10,t+1/10]. Now, we can make the circuit C′′ deterministic. Define the circuit C′′′ as follows. The top symmetric gate g has fan-in 2rh, and the symmetric function is H:[2rh]{0,1}, defined by H(z)=H([12rz]), where [] denotes the closest integer function. The circuits Ci,σ feed into g for each i[h],σ{0,1}r. The size of the circuit C′′′ is 2rpoly(s)=2polylog(n)2polylog(s) without counting the bottom layer and is 2r(poly(s)+2nlog(s)polylog(n,M))=2polylog(s)2polylog(n)+2polylog(s)2nlog(s)polylog(n,M) in total. Note that this step can also be completed in 2polylog(s)2polylog(n)+2polylog(s)2nlog(s)polylog(n,M) time.

Step 2c.

Now, we perform transformation 3 and transformation 4 on C′′′ to get a new deterministic circuit C′′′′. As earlier, these transformations leave the bottom layer of 𝖠𝖭𝖣 gates untouched. The 𝖠𝖭𝖣 gates of C′′′ are pushed to the bottom layer, and the 𝖬𝖮𝖣p gates get absorbed into the symmetric function. Let s′′′ be the size of the 𝖠𝖢𝖢0 part of C′′′. There exists a function f: such that the 𝖠𝖢𝖢0 part of C′′′ is replaced with a 𝖲𝖸𝖬+ circuit with size 2logf(d1)(s′′′). This transformation takes 2logf(d1)(s′′′) time and given the number of input wires that evaluate to 1, the symmetric function itself can be computed in time 2logf(d1)(s′′′). As before, the bottom layer of 𝖠𝖭𝖣 gates remains untouched. All the previously defined polynomial factors do not depend on the depth of the circuit. Hence, we can define a function c: such that the final circuit is a 𝖲𝖸𝖬+ circuit with 2logc(d)s+2loges2n(lognlogM)e wires, for a fixed absolute constant e that can be chosen to absorb all the polynomial factors.

Using this lemma, we can efficiently evaluate a 𝖲𝖸𝖬𝖠𝖢𝖢03-𝖯𝖳𝖥 circuit C of size s on all inputs:

  1. 1.

    Use Lemma 22 to convert C to a 𝖲𝖸𝖬+ circuit D of size S=2logc(d)s+2loges2n(lognlogM)e) in time 2logc(d)s+2loges2n(lognlogM)e).

  2. 2.

    Define the matrices A{0,1}2n/2×S,B{0,1}S×2n/2 as follows. The rows of A and the columns of B are indexed by partial assignments to the first half and second half of the variables respectively. The columns of A and the rows of B are indexed by the 𝖠𝖭𝖣 gates of D. For each 𝖠𝖭𝖣 gate g in the circuit D and partial assignment x to the first n/2 coordinates, define A(x,g) to be 1 if x does not falsify g and 0 otherwise, and for each partial assignment y to the second n/2 variables, define B(g,y) to be 1 if y does not falsify g and 0 otherwise. The matrix M=AB is a 2n/2×2n/2 matrix with rows and columns indexed by partial assignments to the first and second halves of the variables such that M(x,y) is the number of input wires to the top symmetric gate of D set to 1 by the assignment x,y.

  3. 3.

    Evaluate the symmetric function on each entry of the matrix M. This can be done in time O(2n+S), by pre-evaluating the symmetric function H on all i[h], where h is the fan-in of the top symmetric gate in D, and then using this as a lookup table to compute H(M(x,y)) for each x,y{0,1}n/2.

Choosing 𝜺(𝒅),𝜹

If s2nε(d) and M2nδ, then logSnε(d) and logMnδ, which implies that S2nε(d)c(d)+2eε(d)2n(nδlogn)e. Hence, if we pick δ=110e and ε(d)=min{12c(d),110e}, then S<20.05n, which implies that step 2 can be done in time O(2n) using Coppersmith’s algorithm, and step 3 takes time O(2n). This proves Theorem 19.

References

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