-Algorithms for Classes of Threshold Circuits Based on Probabilistic Rank
Abstract
There is a large body of work that shows how to leverage lower bound techniques for circuit classes to obtain satisfiability algorithms that run in better than brute-force time [24, 38]. For circuits with threshold gates, there are several such algorithms based on either
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Probabilistic Representations by low-degree polynomials, which allow for the use of fast polynomial evaluation algorithms, or
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Low rank, which allows for an efficient reduction to rectangular matrix multiplication.
In this paper, we use a related notion of probabilistic rank to obtain satisfiability algorithms for circuit classes contained in , i.e. constant-depth circuits with modular counting gates and a single layer of degree- polynomial threshold functions.
Even for the special case of a single , it is not clear how to use either of the above two strategies to get a non-trivial satisfiability algorithm. The best known algorithm in this case previously was based on memoization and yields worse guarantees than our algorithm.
Keywords and phrases:
probabilistic polynomials, probabilistic rank, circuit satisfiability, circuit lower bounds, polynomial method, threshold circuitsFunding:
Nutan Limaye: Received funding from the Independent Research Fund Denmark (grant agreement No. 10.46540/3103-00116B) and is also supported by the Basic Algorithms Research Copenhagen (BARC), funded by VILLUM Foundation Grants 16582 and 54451, and Digital Research Centre Denmark, project P40.Copyright and License:
2012 ACM Subject Classification:
Theory of computation Computational complexity and cryptographyEditors:
Paweł Gawrychowski, Filip Mazowiecki, and Michał SkrzypczakSeries and Publisher:
Leibniz International Proceedings in Informatics, Schloss Dagstuhl – Leibniz-Zentrum für Informatik
1 Introduction
Satisfiability algorithms and lower bounds
Given a family of circuits a fundamental algorithmic question one can ask about it is the satisfiability question: does a given have a satisfying assignment? This being a canonical -complete problem even for very simple , it is hard to imagine a polynomial-time algorithm for this problem. However, it is still reasonable to try to obtain some speed-up over brute-force search. Typically, and also in this paper, we aim for running times of where denotes the number of variables and is the “savings” over brute-force search.111The trivial algorithm evaluates the circuit on every input, which takes time at least
A long line of work has leveraged structural understanding from complexity-theoretic research on circuit lower bounds to devise satisfiability algorithms for various families of circuits. For example, these ideas have led to approaches to satisfiability algorithms for constant-depth circuit classes [24, 17, 37, 25], Boolean formulas [29, 30] and Threshold circuits of various kinds [34, 12, 18, 9, 7].
A profound result of Williams [36, 38] also makes a connection in the opposite direction, by showing that satisfiability algorithms with savings for many “reasonable” circuit classes implies lower bounds for these classes.222i.e. a superpolynomial improvement over brute-force This gives even more impetus to studying the satisfiability problem in this regime.
Lower bound techniques in satisfiability algorithms
There are a handful of techniques from complexity-theoretic investigations that are useful in devising satisfiability algorithms. These include
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Memoization: In the setting of lower bounds, this idea goes back to the work of Nechiporuk [22] who used it to show quadratic Boolean formula lower bounds. This idea can also be used to obtain satisfiability algorithms in some settings (see e.g. [28, 7]). To apply this technique to a circuit class , one must be able to prove a strong upper bound on the number of functions in of a given size. Unfortunately, in most algorithmic settings (e.g. CNF formulas of unbounded width), one cannot get a strong enough upper bound of this form to get much out of this technique.
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Restriction-based techniques: A popular family of techniques used to devise satisfiability algorithms is the idea of restricting a subset of the variables (i.e. setting them to Boolean assignments) in a way that simplifies the underlying circuit and allows us to circumvent having to try all settings of the other variables. This leads to DPLL-style algorithms for SAT and their extensions to circuits [17] and Boolean formulas [29] based on results such as the Håstad Switching Lemma [15, 16]. Unfortunately, these arguments do not extend to circuit classes where the gate set contains gates other than the DeMorgan basis (e.g. XOR gates or Majority gates that count the number of s) unless severe size restrictions are placed on the circuits [12, 18].
This brings us to the topic of this paper, where we study circuits with threshold gates. For an integer , a Polynomial Threshold Function (PTF) of degree is defined to be a Boolean function such that there exists a multilinear polynomial of degree with integer coefficients such that for each , if and only if . We denote by the class of polynomial threshold functions of degree The special case is denoted
Even the problem of checking if a given is satisfiable is an -complete problem.333Here, the input is given as a polynomial with integer coefficients that represents in the sense described above. Further, the problem for is a considerable generalization of the problem of optimizing a MAX--CSP over Boolean variables. While we know algorithms for MAX--CSP with savings [35], obtaining such a result even in the case of -CSPs remains an elusive problem. For the best known result for see the work of Alman, Chan, and Williams [3].
We will consider algorithms for classes of polynomial-sized circuits using PTF gates (and also other counting gates). In such situations, neither memoization nor restriction-based techniques seem to be useful in devising satisfiability algorithms, except in very special cases (as we will explain below). However, there are some known algorithms that work for such circuit classes. Mostly, they exploit the following ideas.
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Polynomial representations: This is a powerful circuit-analysis technique going back to a foundational circuit lower bound due to Razborov [26, 32] and follow-up results of Yao [39] and Beigel and Tarui [8] which were aimed towards proving bounds for constant-depth circuits with AND, OR, NOT and modular counting gates. Here, it is shown that small circuits from this class can be represented by (sometimes randomized) polynomials. By making this technique algorithmic and using fast polynomial evaluation algorithms, Williams [38] devised the first satisfiability algorithms for these circuits with non-trivial savings, leading also to his breakthrough circuit lower bound for the class
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Rank techniques: Another powerful idea is to reduce the problem of checking satisfiability to computing the entries of a low-rank matrix. Typically, this is done by splitting the variables into two subsets of size and showing that the -sized matrix obtained by evaluating the given input circuit on all pairs of inputs is (a simple function of) a low-rank matrix. By using fast algorithms for rectangular matrix multiplication [14, 34], this leads to satisfiability algorithms for classes such as .
In this work, we show how to extend these ideas to polynomial threshold functions of degree up to and generalizations thereof. It is unclear if either of the above techniques can be used directly to obtain non-trivial savings in this setting.444It should be noted that a PTF of degree has a low-degree polynomial (sign) representation by definition. However, this alone is not enough to devise a satisfiability algorithm. We also need a low-degree polynomial representation for a disjunction of superpolynomially many PTFs, and whether this stronger property holds is unclear. In fact, it seems unlikely [31]. More precisely, we obtain the following results. See Section 2 for definitions.
Theorem 1 (Informal).
We have the following satisfiability algorithms.
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For any fixed prime , a deterministic algorithm for counting the number of satisfying assignments of a given polynomial-sized circuit with savings over brute-force search.
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A deterministic algorithm for counting the number of satisfying assignments of a given polynomial-sized circuit with savings where depends on the depth of the circuit.
Even in the case of a single the running time of our algorithm beats the best-known previous algorithm of [7], which was based on memoization and yielded savings of Moreover, as mentioned above, the technique of memoization does not seem to be useful even for simple extensions of this class to, say, conjunctions of polynomially many -PTFs.
Main idea
The main idea behind our algorithm is similar to the idea used in the work of Alman, Chan and Williams [3] for MAX-4-CSPs. Specifically, we combine the two techniques mentioned above into a probabilistic rank upper bound for the classes of circuits we consider. For simplicity, consider the case when the input is a polynomial of degree representing a -PTF and we want to know if is satisfiable.
As above, we split the Boolean variables of into two disjoint sets and of size and consider the matrix of size where the rows and columns are labelled by settings to variables indexed by and respectively and
for each Now, while we cannot argue that is low-rank, we can argue that there is a low-rank (roughly ) random matrix that agrees with in each entry w.h.p. To do this, we write
| (1) |
by noting that each monomial in must have degree at most either in the variables indexed by or by Partitioning the monomials that have variables in both parts according to choice of this “special” variable gives the decomposition above ( and contain the monomials that contain variables indexed by only one of or respectively). This type of decomposition is exactly like that obtained by [3]. From this point on our proof outline is also quite similar. The main place where we differ is that we need to handle weights which are not necessarily polynomially bounded.
We continue as follows. Note that can be written as the sign of the above expression. To express as a low-rank matrix (probabilistically), we use constructions of probabilistic polynomials (see definition in Section 2) for the Majority function555This idea works when the coefficients of the underlying polynomial are all polynomially small. Our algorithm can also handle coefficients that are exponentially large. In this case, we need some additional circuitry to simulate the sum efficiently. This can be converted to a low-degree polynomial using the construction of Razborov [26, 25]. and variants [6, 3] which allows us to write the above as a random polynomial of degree at most over the bits of the numbers
Each monomial in the polynomial defines a rank- matrix, as it is a product of the form for some functions and . A polynomial of degree thus defines a matrix of rank
To extend the above to (say) we compose the above construction with standard low-degree polynomial representations of the class [2, 8].
This structural result shows that the family of degree- PTFs has low probabilistic rank. This may be of independent interest. Alman and Williams [5] proved such a result for the inner product function, resulting in improved bounds on the rigidity of the Hadamard matrix. Follow-up results have used this idea to give better circuits for computing the Walsh-Hadamard transform [4].
For the satisfiability algorithm, we need to combine this idea with the standard “blow-up trick” of Williams. Returning to the case of a single -PTF we will apply the above idea to
(Note that is satisfiable if and only if is satisfiable.) For suitably small (roughly ), we will apply the above idea to and show that the analogous matrix has low-rank. By using Coppersmith’s rectangular matrix multiplication algorithm [14, 34], it follows that can be computed in time approximately , leading to savings for our algorithm.
Finally, to count the number of satisfying assignments, we replace the OR above by a sum and use similar ideas (as in [34, 25]).
Remark 2.
The algorithm for MAX-d-CSP (for the dense case) by [3] is closely related to our algorithm. They are able to make it work for , whereas, we only obtain algorithms for -PTF. The main bottleneck seems to be that we are dealing with arbitrary weights, whereas they work with polynomially bounded weights. It is unclear how we can make their ideas work even for a single -PTF with arbitrary weights.
Another reason our result does not work for -PTFs for is that the analogous decomposition to (1) yields a decomposition with terms, and the probabilistic degree of the Majority function on variables is [26]. Thus, we only get a polynomial of degree , which does not yield a suitably non-trivial bound on the probabilistic rank of these PTFs. It is an interesting open problem to see if any non-trivial upper bounds can be obtained for the probabilistic rank of PTFs of larger degree.
Related work
Over the past decade, there have been many works studying satisfiability algorithms for circuits using threshold gates and modular counting gates.
In the setting of , the class of constant-depth circuits using AND, OR, NOT and modular counting gates, the first non-trivial satisfiability algorithms were given by Williams [38] followed by improvements in [34], which also yields algorithms for the class Further extensions have been obtained by works of [3, 11] but neither of these works allow us to replace the LTF gates by PTFs of higher degree.
For a single , the best known algorithms use the memoization technique and have savings [27, 7] This technique is grounded in the fact that the number of degree- PTFs on variables is [13], and this does not extend even to simple combinations of PTFs, such as conjunctions of polynomially many PTFs (or even LTFs).666For example, it is easy to show that the number of distinct functions that can be written as a conjunction of LTFs is always at least as long as
There are also restriction-based satisfiability algorithms for circuits made up of LTF and, more generally, PTF gates [12, 18]. Unfortunately, though, these algorithms only work when the size of the circuits (defined in terms of the number of wires) is slightly superlinear in the number of variables.
Paper organization
In Section 3, we upper bound the probabilistic rank of s (Lemma 14) and present a deterministic SAT algorithm for circuits (Theorem 17). In Section 4, we present a SAT algorithm for circuits (Theorem 20).
2 Preliminaries
Computational model and asymptotic notation
All our algorithms can be implemented in the standard RAM model. The notations are used to denote arbitrary, but fixed polynomial and polylogarithmic factors in respectively. We use the and notation to suppress polynomial and logarithmic factors respectively.
The bit complexity of representing ’s
A polynomial threshold function can be defined using multiple polynomials. Hence, the number of bits needed to represent a depends on the bit complexity of the polynomial used to define it.
Definition 3 (Bit complexity of a polynomial).
Given a multilinear polynomial , the bit complexity of is defined to be .
It is known that any can be represented using a polynomial with bit complexity upper bounded by [20]. However, given an arbitrary , it is not clear how to efficiently obtain such a low weight representation. Nevertheless, our algorithms in Section 3 can handle ’s represented by polynomials with bit complexity up to , for some fixed . For the purpose of proving lower bounds, we can always assume that the bit complexity of functions is upper bounded by .
Boolean circuits
We use the standard definitions for boolean circuits and circuit classes. We refer the reader to [33] for more details. The size of a circuit is defined to be the number of wires and its depth is defined to be the total number of layers. The circuit class consists of constant depth circuits with gates of unbounded fan-in. For any , a gate with fan-in outputs if the sum (over ) of its inputs is divisible by and outputs otherwise. For any prime , the class consists of circuits with and gates with unbounded fan-in. The class is defined as circuits of constant depth consisting of and gates of unbounded fan-in, for any fixed composite number .
We define the following class of circuits, which can efficiently represent circuits [1, 2, 8].
Definition 4 (Symmetric functions and circuits).
A boolean function is called a symmetric function if there exists a function such that . A circuit is a depth two boolean circuit with an output gate that computes any symmetric function, and gates at the second layer.
We also use modulus amplifying polynomials in our algorithms for satisfiability.
Definition 5 (Beigel-Tarui modulus amplifying polynomials [8]).
Let be any prime. For any , the -th Beigel Tarui modulus amplifying polynomial is defined as
This polynomial has the property that for all , if and if .
Probabilistic matrices and polynomials
We review some facts on probabilistic matrices and probabilistic polynomials.
Definition 6 (Probabilistic Polynomial).
Let be a field. A probabilistic polynomial over variables is a distribution of polynomials from . An -error probabilistic polynomial for a Boolean function is a probabilistic polynomial such that, for every , . A probabilistic polynomial is said to have degree if .
To derandomize algorithms that use probabilistic polynomials, we will need to design probabilistic polynomials that can be sampled using less randomness. To be precise, we say that a probabilistic polynomial can be sampled in time using bits of randomness if there exists a deterministic algorithm that takes as input a string and in time outputs polynomials, such that for each polynomial , . We will also need to reduce the error of a probabilistic polynomial to any arbitrary .
Lemma 7 (Randomness efficient error reduction for probabilistic polynomials).
Let be any boolean function on variables with an -error probabilistic polynomial of degree that can be sampled using bits of randomness in time . Then, for any there exists a probabilistic polynomial for with error , and degree . Furthermore, is of the form , where are probabilistic polynomials of degree , and there exists an algorithm that uses bits of randomness and outputs as sums of monomials in time .
Proof.
We refer the reader to the proof of [25, Lemma 16].
The notion of probabilistic matrices and probabilistic rank generalize the notion of probabilistic polynomials and probabilistic degree.
Definition 8 (Probabilistic matrix [5]).
Let be any ring. Consider any matrix . A probabilistic matrix for with error is a distribution over matrices in such that for each , . A probabilistic matrix has rank if every matrix sampled from has rank at most . A matrix has -probabilistic rank if there exists a probabilistic matrix for with error and rank .
Fast rectangular matrix multiplication
All our satisfiability algorithms rely on the fact that we can rapidly multiply rectangular matrices using Coppersmith’s algorithm.
Lemma 9 (Coppersmith’s algorithm [14, 34]).
For sufficiently large and and any field with elements, there exists an algorithm that takes matrices as inputs and outputs the matrix in time
We refer the reader to the appendix of [34] for a proof.
3 The probabilistic rank of s
We start with recalling that there exist probabilistic polynomials for circuits with degree polylogarithmic in the size of the circuit.
Lemma 10 (Randomness efficient probabilistic polynomials for [25]).
Let be any prime. Any circuit of depth and size on variables has an -error probabilistic polynomial over the field of degree , and a polynomial can be sampled from the distribution in time and using random bits.
Lemma 11.
There exists a probabilistic polynomial for any symmetric boolean function of error and degree . A polynomial can be sampled from the distribution in time using random bits.
Proof.
Let be the set of all such that if . Hence, . The predicate can be computed by a circuit with gates with fan-in. Now, has a -error probabilistic polynomial over any field of degree , and a polynomial can be sampled from the probabilistic polynomial using random bits [3]. The gates can be converted into polynomials of degree two trivially. Hence, using Lemma 7, we can sample a probabilistic polynomial of error for the predicate of degree using random bits. Finally, we can convert the top gate into a probabilistic polynomial of constant degree and error using random bits (Lemma 10). Setting for the gates and composing these polynomials, we get a probabilistic polynomial for the symmetric function of degree using random bits and error .
Lemma 12.
There exists an circuit with gates that takes as input integers of bits each and outputs their sum.
Proof.
Suppose the bit numbers are , where , with . Let . Let . For each , let . There exist functions such that for each . Then, we can rewrite the sum as follows.
Switching the order of the summation, this is equal to . For each and , the function can be implemented using a single gate with fan-in . Hence, the numbers can be computed in parallel, for each as bit strings of length using a layer of gates of fan-in . What remains is to compute . It is known that addition of numbers with bits each can be implemented using constant depth circuits of size [33]. We can use these circuits with to prove the lemma.
Remark 13.
A very similar -circuit for this problem was first constructed in [19]. However, their construction yields gates of fan-in . The results in this section require circuits with gates with fan-in at most .
Lemma 14.
Let be any prime and be a defined by a polynomial and bit complexity upper bounded by . Then there exist functions , with and a probabilistic polynomial of degree , such that for each ,
Given , and can be computed in time and a polynomial can be sampled from using random bits in time .
Remark 15.
This implies that there exists an absolute constant such that s defined using polynomials of bit complexity upper bounded by have probabilistic degree . In several situations, it may also be reasonable to assume that , as noted in Section 2.
Proof.
Note that any cubic polynomial can be decomposed in the following fashion.
for quadratic polynomials . We can now define and to be the bits of the integers and (with an extra bit to store the sign) for each respectively. The number of bits needed to express and is upper bounded by and respectively. By the definition of bit-complexity of a polynomial, the values of are upper bounded by and hence by for each , which means that and are bit strings of length .
Converting into a sized circuit.
We can define a circuit , which is very similar to the circuit described in the proof of [34, Theorem 1.4] Let denote a circuit that takes as input up to natural numbers with bit complexity and outputs their bit sum. Let denote a circuit that takes as input two bit integers and outputs if and otherwise. The bottom-most layer of the circuit consists of gates with fan-in two. This layer outputs the bits for , . Now, given the bits of the integers for all , we can compute the output of the using a circuit. This can be accomplished by adding up all the negative and positive integers in parallel using two subcircuits and then comparing the outputs of these two subcircuits using an subcircuit. Now, we note that has sized circuit of depth (see [10] and [37, Appendix A] 777this follows from the following fact: , where if and only if .) and has a circuit with gates by Lemma 12. Hence, has gates.
Converting into a probabilistic polynomial.
The next step is to convert into a probabilistic polynomial . Each of the gates at the bottom can be trivially represented by a constant degree polynomial. Next, we convert each symmetric gate into a probabilistic polynomial of error for sufficiently large and degree and monomials using Lemma 11. We can use union bound to show that that the probability that any of the polynomials for the symmetric gates err is upper bounded by . The remaining part of is an circuit with gates. This can be converted into a probabilistic polynomial of degree , inputs and error . Hence, has degree . We can then use Lemma 7 obtain a probabilistic polynomial with error and degree for any .
Randomness and time complexity.
The amount of random bits needed for the probabilistic polynomials for the symmetric gates is (Lemma 11). Because we are using the union bound, we can just reuse the same random bits for all the symmetric gates. The probabilistic polynomials for the part of can be constructed using random bits (Lemma 10). Lemma 14 implies that all functions have low probabilistic rank.
Corollary 16.
functions over variables have probabilistic rank .
Proof.
Any function can be defined using a cubic polynomial with bit complexity [20]. Hence, we can use Lemma 14 to define probabilistic matrices for such that for each , . We can sample matrices from the distributions as follows. We first sample a polynomial from the distribution defined in Lemma 14. The columns of (and the rows of ) are indexed by monomials in . Define the entry of defined by a monomial for a set and an assignment to be , and the entry of defined by the same monomial and an assignment to be , where and denote the -th entry of the strings and respectively. Hence, , which is equal to with probability at least . We use Lemma 14 to obtain a satisfiability algorithm for -SAT, as well as for more expressive complexity classes involving gates. The following theorem follows directly from combining Lemma 14 with Lemma 10 and derandomization techniques developed in [25] to design a deterministic SAT algorithm for circuits.
Theorem 17.
Let be any prime number. There exists a deterministic algorithm that counts the number of satisfying assignments to circuits of depth in time .
Remark 18.
This algorithm can handle circuits of size up to , for some that depends on as well as circuits with s defined by polynomials with weights upper bounded by , for the previously defined .
Proof.
We start with designing a probabilistic polynomial for . Let be the gates in , for . Using Lemma 14, design probabilistic polynomials with monomials and functions , such that . The polynomials can be sampled using a common set of random bits, using Lemma 14 and Lemma 7. We can sample a probabilistic polynomial of error for the part of of degree and random bits using Lemma 10. Composing these polynomials and using Lemma 7 again, we can obtain a probabilistic polynomial with monomials using bits of randomness and functions such that . Furthermore, , for probabilistic polynomials with monomials and .
The satisfiability algorithm now follows from a standard approach to designing circuit satisfiability algorithms, first used by Williams [38] for satisfiability algorithms. Later on, in [25], this algorithm was derandomized and extended to count the number of satisfying assignments. Pick some , and let . For each , let . For each , let denote the circuit , with the first variables restricted according to the assignment . By definition,
and . Now, for each , define functions and probabilistic polynomials on variables such that using Lemma 14. These can be sampled using common random bits. For each , let for denote the polynomial sampled from using the string as the random bits. Hence,
Summing over all ,
| (2) |
where the sum is over , not .
Fourier coefficients
Letting be a function from 888We just let be the standard majority function on , and arbitrarily set it to (say) on all other , we can define coefficients for each , such that . The quantity is interpreted as a real number. The numbers can be computed for each in time using the FFT algorithm. We refer the reader to [23] for more details. Define the polynomials , and let denote the -th Beigel-Tarui modulus amplifying polynomial (Definition 5).
The parameters
Set for a suitable polynomial . Let We remind the reader that and that for constants . We choose . Now, we can present the deterministic algorithm.
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1.
Calculate the coefficients for each for .
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2.
For each , construct the polynomials as sums of monomials and functions , using Lemma 14.
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3.
For each , construct as a sum of monomials, the polynomial
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4.
For each , evaluate using Coppersmith’s algorithm.
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5.
Output (where denotes the nearest integer function).
Running time
Step 1 takes time , which can be upper bounded (very loosely) by . Step 2 takes time , which can be upper bounded by as well. To upper bound the complexity of Step 3, note that has monomials. Choosing the polynomial appropriately, this can be upper bounded by . Hence, we can construct the polynomial for each in time . Because the number of monomials in is upper bounded by , Step 4 takes time (Lemma 9). Step 5 runs in time as well.
Correctness
From the properties of the modulus amplifying polynomials (Definition 5), if , and if . Because we have chosen such that ,
Note that all summations above are over unless they are enclosed by brackets. Now, consider the quantity . Using Section 3, . Hence, . Because , the algorithm indeed outputs .
4 SAT algorithms for circuits
In this section, we show that Lemma 14 an be combined with with well known techniques [1, 2, 38] for simplifying circuits to design SAT algorithms.
Notation
We say that a circuit has parameters if it has inputs, wires, and contains gates defined by polynomials with bit-complexity upper bounded by .
We present a better than brute force algorithm to evaluate circuits on all inputs.
Theorem 19.
There exists an absolute constant and a function such that the following holds. There exists a deterministic algorithm that takes as input a circuit with parameters such that that can enumerate all satisfying assignments to in time .
Using the approach developed in [34] for reducing SAT to rapid evaluation of large circuits of all inputs, we can design a SAT algorithm for circuits. We refer the reader to the proof of [34, Theorem 1.2].
Theorem 20.
There exists an absolute constant and a function such that the following holds. There exists a deterministic algorithm that takes as input an circuit with parameters such that that can count the number of satisfying assignments to in time .
Using [21, Theorem 1.2], we can infer the following circuit lower bound, which is an extension of [21, Theorem 1.3].
Corollary 21.
For every constant , there exists and a problem in which does not have circuits with gates of depth and size .
The rest of this section is devoted to the proof of Theorem 19. The first step is to convert circuits into equivalent circuits.
Lemma 22.
There exists a function and an absolute constant such that the following holds. Let be any circuit with parameters . Then, there exists a circuit and functions such that for each , . The circuit has size , and there exists a deterministic algorithm that takes as input and outputs in time . The functions and output strings of length and are computable in time . The output of the symmetric gate can be computed in time , given the number of input wires that evaluate to .
Proof.
Let denote the symmetric gate at the top, with fan-in , and let be the symmetric function it computes. Let , for denote the subcircuits of that feed into the top gate.
Step 1: Replace the gates with probabilistic polynomials.
Suppose that has gates in the bottom layer, where . Let , and construct probabilistic polynomials with error for each of the gates, with functions such that for each , using Lemma 14. Note that each polynomial can be represented as an circuit, of size at most . Hence, we can replace the circuit with a probabilistic circuit of size , depth such that for each , with probability at least .999Technically, this is not an circuit as it contains gates as well as gates, but rest of the transformations will work for this circuit as well. The fan-in of the gates at the bottom is upper bounded by and the number of gates is upper bounded by . Note that if the wires from the gates at the bottom layer to the rest of the circuit are not counted, has size , and that the polynomials and hence the circuit can be sampled using random bits.
Step 2: Replace the circuit with a deterministic circuit.
Step 2a.
Apply transformation 1 to the circuit . This transformation only acts on the part of and leaves the bottom layer of gates untouched. The gates for composite are eliminated and replaced by subcircuits with prime modulo gates and gates. Further, all the and gates are all replaced by fixed depth circuits with only gates with fan-in and gates (for some prime number ). All these gates share a common set of probabilistic inputs. Let the new circuit be , and let be the subcircuits that feed into the symmetric gate . The circuit has size , without counting the bottom layer. Over the probabilistic inputs as well as the random bits used to sample the probabilistic polynomials, . This step takes time.
Step 2b.
Let denote the number of random bits needed in total to sample . For each , let denote the circuit sampled using the string as the random bits, and let for denote the corresponding subcircuits that feed into the top gate. Now ,suppose that . For each , if and if , Hence, . Now, we can make the circuit deterministic. Define the circuit as follows. The top symmetric gate has fan-in , and the symmetric function is , defined by , where denotes the closest integer function. The circuits feed into for each . The size of the circuit is without counting the bottom layer and is in total. Note that this step can also be completed in time.
Step 2c.
Now, we perform transformation 3 and transformation 4 on to get a new deterministic circuit . As earlier, these transformations leave the bottom layer of gates untouched. The gates of are pushed to the bottom layer, and the gates get absorbed into the symmetric function. Let be the size of the part of . There exists a function such that the part of is replaced with a circuit with size . This transformation takes time and given the number of input wires that evaluate to , the symmetric function itself can be computed in time . As before, the bottom layer of gates remains untouched. All the previously defined polynomial factors do not depend on the depth of the circuit. Hence, we can define a function such that the final circuit is a circuit with wires, for a fixed absolute constant that can be chosen to absorb all the polynomial factors.
Using this lemma, we can efficiently evaluate a circuit of size on all inputs:
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1.
Use Lemma 22 to convert to a circuit of size in time .
-
2.
Define the matrices as follows. The rows of and the columns of are indexed by partial assignments to the first half and second half of the variables respectively. The columns of and the rows of are indexed by the gates of . For each gate in the circuit and partial assignment to the first coordinates, define to be if does not falsify and otherwise, and for each partial assignment to the second variables, define to be if does not falsify and otherwise. The matrix is a matrix with rows and columns indexed by partial assignments to the first and second halves of the variables such that is the number of input wires to the top symmetric gate of set to by the assignment .
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3.
Evaluate the symmetric function on each entry of the matrix . This can be done in time , by pre-evaluating the symmetric function on all , where is the fan-in of the top symmetric gate in , and then using this as a lookup table to compute for each .
Choosing
If and , then and , which implies that . Hence, if we pick and , then , which implies that step 2 can be done in time using Coppersmith’s algorithm, and step 3 takes time . This proves Theorem 19.
References
- [1] Eric Allender and Vivek Gore. On strong separations from . In International Symposium on Fundamentals of Computation Theory, pages 1–15. Springer, 1991. doi:10.1007/3-540-54458-5_44.
- [2] Eric Allender and Vivek Gore. A uniform circuit lower bound for the permanent. SIAM J. Comput., 23(5):1026–1049, 1994. doi:10.1137/S0097539792233907.
- [3] Josh Alman, Timothy M. Chan, and R. Ryan Williams. Polynomial representations of threshold functions and algorithmic applications. In Irit Dinur, editor, IEEE 57th Annual Symposium on Foundations of Computer Science, FOCS 2016, 9-11 October 2016, Hyatt Regency, New Brunswick, New Jersey, USA, pages 467–476. IEEE, IEEE Computer Society, 2016. doi:10.1109/FOCS.2016.57.
- [4] Josh Alman and Kevin Rao. Faster walsh-hadamard and discrete fourier transforms from matrix non-rigidity. In Barna Saha and Rocco A. Servedio, editors, Proceedings of the 55th Annual ACM Symposium on Theory of Computing, STOC 2023, Orlando, FL, USA, June 20-23, 2023, pages 455–462. ACM, 2023. doi:10.1145/3564246.3585188.
- [5] Josh Alman and R. Ryan Williams. Probabilistic rank and matrix rigidity. In Hamed Hatami, Pierre McKenzie, and Valerie King, editors, Proceedings of the 49th Annual ACM SIGACT Symposium on Theory of Computing, STOC 2017, Montreal, QC, Canada, June 19-23, 2017, pages 641–652. ACM, 2017. doi:10.1145/3055399.3055484.
- [6] Josh Alman and Ryan Williams. Probabilistic polynomials and hamming nearest neighbors. In Venkatesan Guruswami, editor, IEEE 56th Annual Symposium on Foundations of Computer Science, FOCS 2015, Berkeley, CA, USA, 17-20 October, 2015, pages 136–150. IEEE, IEEE Computer Society, 2015. doi:10.1109/FOCS.2015.18.
- [7] Swapnam Bajpai, Vaibhav Krishan, Deepanshu Kush, Nutan Limaye, and Srikanth Srinivasan. A #sat algorithm for small constant-depth circuits with PTF gates. Algorithmica, 84(4):1132–1162, 2022. doi:10.1007/s00453-021-00915-7.
- [8] Richard Beigel and Jun Tarui. On ACC. Comput. Complex., 4:350–366, 1994. doi:10.1007/BF01263423.
- [9] Timothy M. Chan. Orthogonal range searching in moderate dimensions: k-d trees and range trees strike back. In Boris Aronov and Matthew J. Katz, editors, 33rd International Symposium on Computational Geometry, SoCG 2017, July 4-7, 2017, Brisbane, Australia, volume 77 of LIPIcs, pages 27:1–27:15. Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2017. doi:10.4230/LIPIcs.SoCG.2017.27.
- [10] Ashok K. Chandra, Larry J. Stockmeyer, and Uzi Vishkin. Constant depth reducibility. SIAM J. Comput., 13(2):423–439, 1984. doi:10.1137/0213028.
- [11] Lijie Chen and R. Ryan Williams. Stronger connections between circuit analysis and circuit lower bounds, via pcps of proximity. In Amir Shpilka, editor, 34th Computational Complexity Conference, CCC 2019, July 18-20, 2019, New Brunswick, NJ, USA, volume 137 of LIPIcs, pages 19:1–19:43. Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2019. doi:10.4230/LIPIcs.CCC.2019.19.
- [12] R Chen, R Santhanam, and S Srinivasan. Average-case lower bounds and satisfiability algorithms for small threshold circuits. Theory of Computing, 14, 2018. doi:10.4086/toc.2018.v014a009.
- [13] Chao-Kong Chow. On the characterization of threshold functions. In 2nd Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1961), pages 34–38. IEEE, 1961. doi:10.1109/FOCS.1961.24.
- [14] Don Coppersmith. Rapid multiplication of rectangular matrices. SIAM J. Comput., 11(3):467–471, 1982. doi:10.1137/0211037.
- [15] Johan Håstad. Almost optimal lower bounds for small depth circuits. In Juris Hartmanis, editor, Proceedings of the 18th Annual ACM Symposium on Theory of Computing, May 28-30, 1986, Berkeley, California, USA, pages 6–20. ACM, 1986. doi:10.1145/12130.12132.
- [16] Johan Håstad. Computational limitations for small depth circuits. PhD thesis, Massachusetts Institute of Technology, 1986.
- [17] Russell Impagliazzo, William Matthews, and Ramamohan Paturi. A satisfiability algorithm for ac. In Yuval Rabani, editor, Proceedings of the Twenty-Third Annual ACM-SIAM Symposium on Discrete Algorithms, SODA 2012, Kyoto, Japan, January 17-19, 2012, pages 961–972. SIAM, SIAM, 2012. doi:10.1137/1.9781611973099.77.
- [18] Valentine Kabanets and Zhenjian Lu. Satisfiability and derandomization for small polynomial threshold circuits. In Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques (APPROX/RANDOM 2018). Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2018. doi:10.4230/LIPIcs.APPROX-RANDOM.2018.46.
- [19] Alexis Maciel and Denis Thérien. Threshold circuits of small majority-depth. Inf. Comput., 146(1):55–83, 1998. doi:10.1006/inco.1998.2732.
- [20] Saburo Muroga. Threshold logic and its applications. John Wiley & Sons, 1971.
- [21] Cody Murray and R. Ryan Williams. Circuit lower bounds for nondeterministic quasi-polytime: an easy witness lemma for NP and NQP. In Ilias Diakonikolas, David Kempe, and Monika Henzinger, editors, Proceedings of the 50th Annual ACM SIGACT Symposium on Theory of Computing, STOC 2018, Los Angeles, CA, USA, June 25-29, 2018, pages 890–901. ACM, 2018. doi:10.1145/3188745.3188910.
- [22] Eduard Ivanovich Nechiporuk. On a boolean function. In Dokl. Akad. Nauk SSSR, volume 169(4), pages 765–766. Russian Academy of Sciences, 1966.
- [23] Ryan O’Donnell. Analysis of Boolean Functions. Cambridge University Press, 2014. URL: http://www.cambridge.org/de/academic/subjects/computer-science/algorithmics-complexity-computer-algebra-and-computational-g/analysis-boolean-functions.
- [24] Ramamohan Paturi, Pavel Pudlák, and Francis Zane. Satisfiability coding lemma. In 38th Annual Symposium on Foundations of Computer Science, FOCS ’97, Miami Beach, Florida, USA, October 19-22, 1997, pages 566–574. IEEE, IEEE Computer Society, 1997. doi:10.1109/SFCS.1997.646146.
- [25] Ninad Rajgopal, Rahul Santhanam, and Srikanth Srinivasan. Deterministically counting satisfying assignments for constant-depth circuits with parity gates, with implications for lower bounds. In Igor Potapov, Paul G. Spirakis, and James Worrell, editors, 43rd International Symposium on Mathematical Foundations of Computer Science, MFCS 2018, August 27-31, 2018, Liverpool, UK, volume 117 of LIPIcs, pages 78:1–78:15. Schloss Dagstuhl – Leibniz-Zentrum für Informatik, Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2018. doi:10.4230/LIPIcs.MFCS.2018.78.
- [26] Alexander A Razborov. Lower bounds on the size of bounded depth circuits over a complete basis with logical addition. Mat. Zametki, 41(4):598–607, 1987.
- [27] Takayuki Sakai, Kazuhisa Seto, Suguru Tamaki, and Junichi Teruyama. Improved exact algorithms for mildly sparse instances of max SAT. Theor. Comput. Sci., 697:58–68, 2017. doi:10.1016/j.tcs.2017.07.011.
- [28] Takayuki Sakai, Kazuhisa Seto, Suguru Tamaki, and Junichi Teruyama. Bounded depth circuits with weighted symmetric gates: Satisfiability, lower bounds and compression. J. Comput. Syst. Sci., 105:87–103, 2019. doi:10.1016/j.jcss.2019.04.004.
- [29] Rahul Santhanam. Fighting perebor: New and improved algorithms for formula and QBF satisfiability. In 51th Annual IEEE Symposium on Foundations of Computer Science, FOCS 2010, October 23-26, 2010, Las Vegas, Nevada, USA, pages 183–192. IEEE, IEEE Computer Society, 2010. doi:10.1109/FOCS.2010.25.
- [30] Kazuhisa Seto and Suguru Tamaki. A satisfiability algorithm and average-case hardness for formulas over the full binary basis. Comput. Complex., 22(2):245–274, 2013. doi:10.1007/s00037-013-0067-7.
- [31] Alexander A. Sherstov. The intersection of two halfspaces has high threshold degree. SIAM J. Comput., 42(6):2329–2374, 2013. doi:10.1137/100785260.
- [32] Roman Smolensky. Algebraic methods in the theory of lower bounds for boolean circuit complexity. In Alfred V. Aho, editor, Proceedings of the 19th Annual ACM Symposium on Theory of Computing, 1987, New York, New York, USA, pages 77–82. ACM, 1987. doi:10.1145/28395.28404.
- [33] Heribert Vollmer. Introduction to circuit complexity: a uniform approach. Springer Science & Business Media, 1999. doi:10.1007/978-3-662-03927-4.
- [34] R. Ryan Williams. New algorithms and lower bounds for circuits with linear threshold gates. Theory Comput., 14(1):1–25, 2018. doi:10.4086/toc.2018.v014a017.
- [35] Ryan Williams. A new algorithm for optimal 2-constraint satisfaction and its implications. Theor. Comput. Sci., 348(2-3):357–365, 2005. doi:10.1016/j.tcs.2005.09.023.
- [36] Ryan Williams. Improving exhaustive search implies superpolynomial lower bounds. SIAM J. Comput., 42(3):1218–1244, 2013. doi:10.1137/10080703X.
- [37] Ryan Williams. Faster all-pairs shortest paths via circuit complexity. In David B. Shmoys, editor, Symposium on Theory of Computing, STOC 2014, New York, NY, USA, May 31 - June 03, 2014, pages 664–673. ACM, 2014. doi:10.1145/2591796.2591811.
- [38] Ryan Williams. Nonuniform ACC circuit lower bounds. J. ACM, 61(1):2:1–2:32, 2014. doi:10.1145/2559903.
- [39] Andrew Chi-Chih Yao. On ACC and threshold circuits. In 31st Annual Symposium on Foundations of Computer Science, St. Louis, Missouri, USA, October 22-24, 1990, Volume II, pages 619–627. IEEE, IEEE Computer Society, 1990. doi:10.1109/FSCS.1990.89583.
