Linear Layouts Revisited:
Stacks, Queues, and Exact Algorithms
Abstract
In spite of the extensive study of stack and queue layouts, many fundamental questions remain open concerning the complexity-theoretic frontiers for computing stack and queue layouts. A stack (resp. queue) layout places vertices along a line and assigns edges to pages so that no two edges on the same page are crossing (resp. nested). We provide three new algorithms which together substantially expand our understanding of these problems:
-
1.
A fixed-parameter algorithm for computing minimum-page stack and queue layouts w.r.t. the vertex integrity of an -vertex graph . This result is motivated by an open question in the literature and generalizes the previous algorithms parameterizing by the vertex cover number of . The proof relies on a newly developed Ramsey pruning technique. Vertex integrity intuitively measures the vertex deletion distance to a subgraph with only small connected components.
-
2.
An algorithm for computing -page stack and queue layouts of page width at most . This is the first algorithm avoiding a double-exponential dependency on the parameters. The page width of a layout measures the maximum number of edges one needs to cross on any page to reach the outer face.
-
3.
A algorithm for computing -page queue layouts. This improves upon the previously fastest algorithm and can be seen as a counterpart to the recent subexponential algorithm for computing -page stack layouts [ICALP’24], but relies on an entirely different technique.
Keywords and phrases:
stack layouts, queue layouts, parameterized algorithms, vertex integrity, Ramsey theoryFunding:
Thomas Depian: Project No. 10.47379/ICT22029 of the Vienna Science Foundation (WWTF).Copyright and License:
2012 ACM Subject Classification:
Theory of computation Parameterized complexity and exact algorithmsEditors:
Anne Benoit, Haim Kaplan, Sebastian Wild, and Grzegorz HermanSeries and Publisher:
Leibniz International Proceedings in Informatics, Schloss Dagstuhl – Leibniz-Zentrum für Informatik
1 Introduction
A linear layout of a graph is a total ordering of its vertices and a partitioning of its edges into pages such that each page satisfies certain conditions. The two by far most commonly studied types of linear layouts are stack layouts and queue layouts; in the former, we require that no four vertices have the edges and placed on the same page, while for the latter we forbid any page from containing the edges and . Intuitively, this corresponds to forbidding edges crossing and edges nesting (in a rainbow pattern), respectively – see Figure 1. ††Due to space constraints, we defer full proofs of statements marked with ★ to the full version [14].
Originally motivated from applications in VLSI [10, 41] and bioinformatics [31], stack and queue layouts have become the focus of extensive research. While there are many classical works studying the structural properties of the two notions [32, 46, 34, 19, 18, 20, 21, 17], several more recent studies have targeted exact and parameterized algorithms for computing stack and queue layouts that minimize the number of used pages. These results are inherently aimed at circumventing the long-known intractability of these problems: the -hardness of determining whether an input graph admits a -page stack layout or a -page queue layout has been established over thirty years ago [46, 34].
To that end, recent works have pursued the use of structural graph parameters to establish tractability on graphs which are “well-structured”. Computing -page stack layouts is now known to be fixed-parameter tractable w.r.t. the vertex cover number [7] or, alternatively, the feedback edge number of the input graph [26]. Computing -page queue layouts is likewise known to admit a fixed-parameter algorithm w.r.t. the vertex cover number of [8]. One drawback of these results is that they only yield tractability under highly restrictive graph parameters, in the sense of achieving low values only on very “simple” graphs. While computing -page queue layouts is also known to be fixed-parameter tractable when parameterized by the treedepth of [8], for general it was repeatedly posed as an open question whether the aforementioned vertex-cover based algorithms can be lifted to less restrictive structural graph parameters [21, 7, 25, 8, 26]. Another recent direction is the establishment of tighter algorithmic upper bounds for special cases: while -page stack and queue layouts can both be computed in time via trivial brute-force algorithms, -page stack layouts are now known to admit a subexponential algorithm [26].
Contributions.
As our first contribution, we lift the aforementioned fixed-parameter tractability of computing linear layouts to a less restrictive structural graph parameter:
Theorem 1.
Computing a minimum-page stack layout and minimum-page queue layout is fixed-parameter tractable w.r.t. the vertex integrity of the input graph.
The vertex integrity of a graph measures, roughly speaking, how many vertex deletions are required to decompose into small connected components, and has been used in the design of parameterized algorithms for a variety of challenging problems [22, 9, 24, 27, 23, 29, 39, 30].111Some prior works use the fracture number, which is parametrically equivalent to vertex integrity. More precisely, is the minimum integer satisfying the following: there exists a vertex set such that for each connected component of , . As vertex integrity is upper-bounded by the vertex cover number plus one, Theorem 1 generalizes the fixed-parameter tractable algorithms for computing stack and queue layouts w.r.t. the vertex cover number by Bhore, Ganian, Montecchiani, and Nöllenburg [7, 8]. Moreover, since the vertex integrity is sandwiched between the vertex cover number and treedepth, our result can be seen as a stepping stone towards solving the problem on more general parameterizations.
To establish Theorem 1, we introduce a novel proof technique we call Ramsey pruning. On a high level, the algorithm underlying the computation is very simple: assuming is larger than some pre-designated function , it recursively identifies a connected component of such that contains sufficiently many copies of , and deletes from the instance. The difficulty lies in proving that this operation is safe, i.e., that does not admit a layout with fewer pages than . The “usual” approach for such a proof would be to show that can be reinserted into any hypothetical linear layout of without increasing the number of pages; however, this not only seems excruciatingly difficult to prove, but we also believe it to be false for certain choices for . Ramsey pruning avoids this issue by using Ramsey-type arguments to argue that must contain a guiding sub-layout – a linear layout of some carefully selected subgraph of – with certain well-defined properties. We then use the well-formedness of to build a brand new linear layout of , thus establishing that and indeed require the same number of pages. We believe this new technique to be generic and applicable to other problems under the same parameterization, as suggested by the fact that unlike the previous vertex-cover based algorithms our approach works for both stack and queue layouts with almost no problem-specific changes required.
While Theorem 1 pushes the frontiers of tractability for our two problems of interest in a complexity-theoretic sense, our use of Ramsey-type arguments means that the obtained running time bound has an entirely impractical dependency on the parameter (see Lemma 5). In fact, up to now none of the known parameterized algorithms for computing -page stack or queue layouts have a runtime parameter dependency that would be better than double-exponential – the parameterized algorithms w.r.t. the vertex cover [7, 8] and feedback edge numbers [26] all preprocess the graph to obtain an equivalent instance (a kernel) whose size is exponential in the parameter, and then solve that equivalent bounded-size instance via brute force. As our second contribution, we provide the first single-exponential algorithms (in the parameters) capable of solving these problems for arbitrary fixed choices of :
Theorem 2 (★).
Given integers and along with an -vertex graph , we can compute an -page stack or queue layout with page width at most of (if one exists) in time .
Here, the page width measures the maximum number of edges one needs to cross to reach any vertex from the outer face (see also Section 2). The page width of linear layouts222The term cutwidth has been used interchangeably with page width in the past [10]; here, we use the latter in order to disambiguate from the related graph parameter cutwidth. has been studied in several early works [10, 32, 43, 44] and it is generally desirable to obtain layouts not only using few pages, but also with low page width – in fact, the original papers introducing stack layouts explicitly targeted algorithms optimizing both measures. However, the algorithmic applications of page width as a parameter have only been investigated in a recent paper on extending incomplete linear layouts [12]. We remark that while Theorem 2 merely provides a so-called algorithm in a complexity-theoretic sense, it may still be more efficient in practice than known fixed-parameter algorithms for the problem – especially if the aim is to compute layouts with low pagewidth.
A natural approach towards establishing Theorem 2 would be to use dynamic programming in order to construct the sought-after linear layout in a “left-to-right” fashion; however, the issue is that doing this directly would require us to store roughly possible subsets of previously processed vertices. To circumvent this, we obtain new insights into the decomposability of layouts with bounded page width, allowing us to construct an -size auxiliary state graph , where we show that the dynamic computation of a sought-after layout can be represented as an easily computable path in .
As our final third contribution, we take a step back from the multivariate analysis of these problems and recall that the trivial barrier was only recently overcome for computing -page stack layouts [26], i.e., the lowest-page stack layouts giving rise to an -complete problem. Here, we show that the trivial barrier can also be overcome when aiming for the lowest-page queue layouts which still give rise to -completeness:
Theorem 3 (★).
Given an -vertex graph , we can compute a -page queue layout of (if one exists) in time .
We remark that the running time bound provided by Theorem 3 is worse than the bound previously obtained for -page stack layouts [26]. The reason for this is that the latter result relied on the equivalence of -page stack layouts with the existence of subhamiltonian paths; the authors of that previous work then essentially obtained a single-exponential fixed-parameter algorithm for finding such paths w.r.t. the graph parameter treewidth, improving on the previously established fixed-parameter tractability of the problem [4].
However, emulating the same approach seems difficult in the queue layout setting: -page queue layouts also have an equivalent formulation in terms of so-called arched-level planar drawings [34], but it is not at all clear whether computing such drawings is fixed-parameter tractable w.r.t. treewidth (not to mention the fact that one would need a single-exponential algorithm). Instead, our proof of Theorem 3 relies on a Turing reduction from computing arched-level planar drawings to many instances of a well-studied problem called Level Planarity, which is known to be solvable in polynomial time [33, 37].
Related Work.
We refer to the dedicated survey for an overview of many earlier structural results concerning linear layouts [19]. Key structural results in the area include the existence of -page stack layouts [46] and -page queue layouts [17, 5] for all planar graphs. Researchers have also studied the notion of mixed layouts, which are linear layouts with some pages behaving like stack and some like queue layouts [3, 38]. We note that due to the techniques used in their proofs, it seems very likely that Theorems 1 and 2 could be adapted to the mixed layout setting with minimum changes required. Finally, we remark that parameterized algorithms for stack and/or queue layouts have additionally been considered in the extension setting (where the task is to complete a provided partial layout) [12, 13], in the upward-planarity setting (where the graph is directed and edges must be oriented in a left-to-right fashion along the layout) [6] and when the vertex ordering in the layout is fixed [40, 1].
2 Preliminaries
For an integer we let denote the set . We assume the reader to be familiar with standard graph terminology [15]. Without loss of generality, we assume all input graphs to be connected, have vertices and edges. For a set of vertices , we let denote the graph induced on . Furthermore, for a set of edges , we let denote the set of its endpoints and . A cut of is a partition of the vertices in and . We call a cut-set of size that induces the cut . Throughout the paper, we omit an explicit reference to if it is clear from the context, e.g., we write and instead of and .
Given a linear order of a graph and two vertices , we say that is left of if and right of if . The vertices and are consecutive on the spine if they occur consecutively in , i.e., there is no vertex such that or holds. We address with all vertices left of with respect to and define . Finally, we let denote the set of edges that span the spine between and its right neighbor, i.e., all edges with one endpoint left of (or at) and one right of .
We assume familiarity with the basic foundations of parameterized complexity theory [11]. All algorithms obtained in this work are exact, deterministic, constructive and rely exclusively on computable functions. To express some of our bounds, we will occasionally use the Knuth notation where for an integer , represents an exponential tower of ’s of height .
Linear Layouts.
Let and be two edges of . We say that they cross under a linear order if holds, and they nest if holds. For an integer , let be a function that assigns each edge to a page . The linear layout is a stack (queue) layout if no two edges with cross (nest). We call the spine order and the page assignment. For the remainder of the paper, we write and if the graph is clear from context.
The page width of an -page linear layout corresponds to the maximum number of edges on a single page that span the spine between a vertex and its right neighbor, i.e., . We call an -page linear layout with page width an -page -width linear layout, or simply a solution when the and are clear from context. In line with the literature, we assume no explicit bound on the page width when is not specified.
Vertex Integrity.
A graph has vertex integrity if is the smallest integer with the following property: contains a vertex set such that for each connected component of , . One may observe that the vertex integrity is upper-bounded by the size of a minimum vertex cover in the graph (i.e., the vertex cover number) plus one. The vertex integrity of an -vertex graph along with a corresponding partition into and can be computed in time [16].
3 A Fixed-Parameter Algorithm Parameterized by Vertex Integrity
In this section, we obtain a fixed-parameter algorithm that takes as input a positive integer and a graph , is parameterized by and computes an -page stack and/or queue layout of (or both), if such layouts exist. We begin by noting that using well-known relationships between vertex integrity, minimum-page stack and queue layouts and the graph parameter treewidth (tw), we can assume to be upper-bounded by a function of thanks to the well-known relation :
Proposition 4 ([20, 45]).
The number of pages in a minimum stack and queue layout of a graph is upper-bounded by and , respectively.
The algorithm operates by obtaining a problem kernel, as formalized below; recall .
Lemma 5.
There is an time algorithm that takes a graph with an integer and outputs a subgraph of (a kernel) of size at most with the following property: admits an -page stack (or queue) layout if and only if so does . Moreover, such a layout for can be computed from in polynomial time.
Lemma 5 directly implies Theorem 1, and the rest of this section is dedicated to proving this lemma. For the following, let us fix a graph , positive integers and , and a choice of witnessing as in Section 2. Further let be the set of connected components of . First, we define a notion of “component-types” which groups components in that exhibit the same outside connections and internal structure.
Definition 6.
We say two graphs are twins, denoted , if there exists a canonical isomorphism from to such that for each vertex and each , if and only if .
Lemma 7 (★).
Each graph has at most vertices, is an equivalence relation and the number of equivalence classes in is upper-bounded by . Moreover, a partition of connected components into can be computed in time at most .
We now introduce the notion of large equivalence classes based on their size. We then use this to define what we call a large group of vertices – one that contains exactly one representative from each large equivalence class. Our kernel will keep a bounded number of these large groups.
Definition 8.
Let be a positive integer, an equivalence class of is said to be -large if . Further a vertex set is called a -large group if the induced subgraph is a disjoint union of exactly one graph from each -large equivalence class of .
Next we define a special induced subgraph that will serve as our kernel. The definition is based on carefully choosing a that is bounded by a computable function of and so that keeping only many -large groups along with the small parts of the graph suffices to capture the necessary structure. Towards this, let us first fix to be a computable function that is large enough to apply our Ramsey-type arguments later on; here, will be an integer that represents the size of a deletion set (initially , but this will be updated iteratively in the proof of Lemma 11). Moreover, let be a computable function of and that will upper-bound our nested application of the function in that same proof; to provide a concrete bound, we set .
Definition 9.
An induced subgraph of is said to be a reduced graph of if there exists a positive integer and a partition of satisfying:
-
1.
and is the set of all vertices in graphs in that do not belong to an -large equivalence class of .
-
2.
If there are no -large equivalence classes of , and . Otherwise, it holds that where is an -large group for each , and each pair of and , , is vertex-disjoint.
Intuitively, the reduced graphs we will be dealing with will consist of , a set of all equivalence classes of which are too small to fully saturate our large groups (these will later be treated essentially in the same way as ), and a sufficient number of large groups; equivalence classes of size larger than are “pruned” to have size exactly . A schematic overview of this intuition can be found in Figures 2b and c later on.
The core of our result is the following lemma, which we prove separately in Section 3.1.
Lemma 10.
If is a reduced graph of then has an -page stack (queue) layout if and only if has an -page stack (queue) layout.
Before proceeding to that proof, we show how to construct a reduced graph having size bounded by a computable function of and in polynomial time.
Lemma 11 (★).
There exists a reduced graph of , and given and such a graph can be computed in polynomial time. Further, the number of vertices in is upper-bounded by .
Lemma 11 combined with Lemma 10 establishes Lemma 5 by constructing a reduced graph which is a kernel of the desired size. Thus, what remains is to establish Lemma 10; this is where the core ideas of Ramsey pruning will come into play.
3.1 Proof of Lemma 10
For this proof, we fix to be a reduced graph of . Since is an induced subgraph of , it is clear that if has an -page stack (queue) layout then also has an -page stack (queue) layout. To complete the proof we show that the reverse is true: If has an -page stack (queue) layout, then also has an -page stack (queue) layout.
Recall that . Let be a fixed (but hypothetical) -page stack (queue) layout of ; throughout this section, for we will use to refer to the sublayout of induced on the subgraph of . If we are done. So let be a partition witnessing that is a reduced graph. Here each is a -large group and is the set of all vertices in graphs that do not belong to an -large equivalence class in . For brevity, we will hereinafter use large as shorthand for -large.
Let . Our key idea is to identify three large groups with a special structure (a “guiding sublayout”) in the solution using Ramsey theory. We will then use this pattern to insert the remaining parts of the graph. Before proceeding, we define some notations to be able to identify these groups, starting with a “template” .
Definition 12.
Let be the number of large equivalence classes in and let be a canonical representative of the large equivalence class . Let .
Recall that by Definition 8, if is a large group then is a disjoint union of exactly one graph from each large equivalence class of . We now define a natural isomorphism from to . This will allow us to map consistently between different large groups via .
Definition 13.
For a large group with , for each , let be an isomorphism from to such that for each and vertex , , and for each , if and only if .
For any large group and for each we will sometimes use as shorthand for . From now we fix two distinct large groups and in . Further, for distinct large groups , we say if in , the first vertex in is from .
Definition 14.
For , we define
-
for each
-
for each
-
for each
Note that is an isomorphism from to .
Definition 15.
For , is the stack (queue) layout of obtained from using the isomorphism .
We are now ready to show the existence of three distinct large groups with a useful consistent pattern between them and based on info. Essentially, these three groups will form the aforementioned guiding sublayout used to argue the correctness of the pruning step, i.e., establish Lemma 10 by showing that we can reinsert all the removed vertices by building on . Note that – perhaps counterintuitively – we will do so by discarding all other information about . We refer to Figure 2 for an overview of the entire approach and to Figure 4 for a visualization of info.
Lemma 16.
There exists distinct large groups with such that .
Proof.
Construct a complete edge colored auxiliary graph with . For with , we set . Let .
Claim 17 (★).
The number of possible distinct edge colors of is at most .
We now use a well-known fact (from Ramsey theory [2]) that any edge-colored clique on vertices colored with colors has a monochromatic clique of size at least .
We have . Thus and and therefore there is a monochromatic clique of size at least . A monochromatic clique of size in corresponds to distinct large groups with such that . Let be three large groups witnessing the previous lemma. We now show that we can partition the vertices of , , and in a nice way that will guide us on how to insert the remaining parts of the graph. Towards this, we first note that the forces (1) edges incident to , and to have the same page assignment, and moreover (2) forces the individual vertex orderings of , , to be exactly the same as some ordering of ; see also the full version [14, Observations 18 and 19]. However, this does not yet fix how the vertices of , and are ordered with respect to each other.
For the following, let us set . Let a block be a consecutive subsequence of vertices from w.r.t. , and a solution-block of be a consecutive subsequence of vertices from ; see also Figure 3.
We are now ready to prove the structural result which provides strong guardrails on ; in particular, it guarantees that all vertices from , and must occur in consecutive solution-blocks and following a strict “ascending” or “descending” order. We remark that this structural result is only made possible by the extraction of three copies of large groups via Lemma 16; see also Figure 4 for an illustration.
Lemma 18 (★).
There exists a pair , where is a partitioning of into blocks and satisfying the following. For every block with , the sequence is a solution-block of . Moreover, for every block with , the sequence is a solution-block of .
Crucially, we can now use Lemma 18 to safely insert an arbitrary number of large groups into without increasing the number of required pages.
Lemma 19 (★).
Let be the supergraph of with each large equivalence class having equal size, then has an -page stack (queue) layout.
Proof sketch..
Let be the maximum size of a large equivalence class of . Note that can be expressed as where each is a large group. We construct a stack (or queue, as desired) layout of as follows.
Construction of .
For each edge ,
-
If , we set .
-
If for some and , we set where .
-
If for some , we set where , .
Construction of .
In , replace each block with if and with if .
To show that is indeed an -page stack (queue) layout of , we show that any conflict in would also imply a conflict in in the full proof [14].
4 An XP-Algorithm For Bounded-Width Linear Layouts
In this section, we present an algorithm to decide if a given graph has a stack (or queue) layout on pages and with page width , i.e., an -page -width linear layout, in time. In the affirmative case, it can also output such a layout. Since only little adaption is required between stack and queue layouts, we only discuss problem specific changes where necessary. We will first give an intuitive overview over our approach and the core ideas to showing its correctness, details can be found in Sections 4.2 and 4.1 and the full version.
Bounded-size Interfaces.
Observe that, for each vertex in a stack (or queue) layout of , the edges that span the spine right next to , induce the cut in ; see Figure 5a. The size of the cut-set only depends on the number of the pages and their width. Our algorithm is centered around the insight that, through limiting these parameters and thus the size of any such cut, we limit the size of the “interface” (a notion we will define more precisely in a second) between a drawing on its left side and a drawing on its right side (Lemma 22). We note that this insight parallels to the approach used by Saxe [42] to test if a graph has bandwidth at most . In our setting, replacing the left side of such cut in any solution drawing with one that provides the same interface will yield another solution. This is because having the same interface will imply inducing the same decompositions into left and right vertices (Lemma 24), the statement then follows by simply gluing the two drawings together along the cut.
Our bounded-size interface consists of the set of edges that intersect the cut right next to , their vertical order along the cut, and the information which edge endpoint lies on which side of the cut, together with a page assignment for the edges in . We will encapsulate this information in what we call a (nicely) oriented cut-set; see Definition 21.
Our Dynamic Programming Solution.
Given only an arbitrary oriented cut-set for an instance , we are able to infer which connected components and thus which vertices of the graph lie on the left (or also right) side of the cut (Lemma 23; see also Figure 5b). This now allows us to solve this problem via dynamic programming. We build a directed acyclic state graph where each state corresponds to one configuration of our interface, i.e. one (nicely) oriented cut-set together with a page assignment for its edges (formalized as C 1 and 2 in the full version [14]). We add an arc between two states if we can move from one oriented cut-set to the other by moving exactly one vertex (which we inferred to be on the right side via Lemma 23) to the (end of a linear order used on the) left without directly violating a necessary stack or queue layout property (i.e., no crossing or nesting of edges) with regard to only the edges in the current cut-set; the exact conditions are again formalized as C 1–4 in the full version [14]. In Lemma 25, we will show that this means that we can extend any partial solution represented by the current state with the further vertex when moving along such an arc to obtain a solution for the new state. Then, we have a yes-instance if and only if there exists a directed path between the (artificially-distinguished) empty beginning and end states. As finding such path takes linear time, Theorem 2 then follows from the insight that the state graph has a size bounded by and can be computed in this time.
4.1 Decomposing Linear Layouts Using Oriented Cut-Sets
As already hinted above, our algorithm uses at its core cut-sets of to compute the desired stack (or queue) layout . Before we discuss their usage in detail, let us first take a closer look at them and define their desired properties.
Observation 20.
Given a connected graph and a cut-set that separates the graph into connected components . For all , component contains at least one vertex that is an endpoint of an edge in .
We consider in addition to a cut-set a total order on the endpoints of its edges and call this the oriented cut-set, denoted as . While a single cut-set has different oriented cut-sets, we are only interested in “nicely oriented” cut-sets. Let be a cut-set and a linear order on the endpoints of edges in . A vertex is a source (or sink) in if for every edge we have (, respectively).
Definition 21.
For a cut-set , is nicely oriented if and only if each vertex is either a source or sink, each connected component of contains either only sources or only sinks, and all sources are left of every sink in .
To ease presentation, we use a slight abuse of notation and allow the linear order of an oriented cut-set to be a total order of a super-set of . We consider and identical if and agree on . We now establish a crucial connection between linear layouts and nicely oriented cut-sets of ; see also Figure 5.
Lemma 22 (★).
Let be a graph and be an -page -width linear layout of . For every vertex that is not the rightmost in , the edges form a cut-set of size at most that induces the cut in . Furthermore, is nicely oriented.
A liner order induces an oriented cut-set if there exists a vertex that witnesses . Note that the same oriented cut-set can be induced by different linear orders. From Lemma 22, we can deduce that all cuts of an -page -width stack (and queue) layout of can be constructed using at most different cut-sets. We aim to use their oriented counterparts to obtain the spine order of the desired stack (or queue) layout. We next show that we can efficiently compute for a given oriented cut-set a witnessing linear order that induces .
Lemma 23 (★).
Given a graph and a nicely oriented cut-set of , we can compute a linear order of that induces in time.
Lemma 23 only shows that we can compute some linear order of that induces . However, to efficiently use oriented cut-sets in our state graph, we must be able to precisely determine which vertices have already been placed on the spine without storing them explicitly. The following lemma lays the foundation for this, as it shows that no matter which linear order we choose to induce an oriented cut-set , we obtain the same partition into left and right vertices.
Lemma 24 (★).
Let be a nicely oriented cut-set. Furthermore, let and be two linear orders such that for some , i.e., they induce . Then we have .
4.2 Using Nicely Oriented Cut-Sets to Show Theorem 2
The state graph contains a node for each possible nicely-oriented cut-set of , together with the corresponding page assignment. The arcs in represent possible transitions from one nicely oriented cut-set to another that can occur when traversing a hypothetical solution from left to right (see Figure 6), i.e., that are obtained by moving exactly one vertex from the right to the left. A state is feasible if and only if there exists an -page -width stack layout of such that for all we have and . For queue layouts, the definition is analogous. In the full version, we show that, essentially, having arcs only between state pairs where both induce valid stack (or queue) layouts on their respective cut-sets is enough to preserve feasibilty along arcs.
Lemma 25 (★).
Let be a state graph and one of its arcs. If is feasible for stack (queue) layouts then so is .
We now have all tools at hand to present our algorithm. Since the arcs of preserve existence of a (partial) -page -width stack (or queue) layout of , we have reduced the problem of finding such a layout to the problem of finding a path in between the two special nodes and . In the full version, we show that can be computed in polynomial time and use this to summarize the main result of this section in the following theorem.
Theorem 2 (★). [Restated, see original statement.]
Given integers and along with an -vertex graph , we can compute an -page stack or queue layout with page width at most of (if one exists) in time .
The algorithm from Theorem 2 runs in polynomial time for constant and . Furthermore, recall that deciding if a graph has a 2-page stack layout or 1-page queue layout is -complete [46, 34]. An -page -width stack or queue layout witnesses that has cutwidth at most , which is in general -complete to decide [28]. This means that under well-established complexity assumptions, it is not possible to preserve -tractability if either of the two parameters is dropped.
5 Single-Exponential Algorithm for 1-Page Queue Layouts
In this section, we show that we can find a one-page queue layout, if it exists, in time, which improves on the trivial algorithm that exhaustively considers all possible spine orders. Our algorithm exploits the equivalence between one-page queue layouts and arched leveled planar embeddings established by Heath and Rosenberg [34]. We first show that we can reduce the problem of deciding whether a graph admits a one-page queue layout to deciding whether at least one of labeled instances of Arched Leveled Planarity admits a solution. While Arched Leveled Planarity is -complete [34], our labeled instances can be solved in linear time thanks to a reduction to the well-studied problem Level Planarity [35, 36]. We will assume that is connected (as each component can be treated separated) and, as must be planar [34], we assume .
We translate the definition of Heath and Rosenberg [34] into moderns terms as follows. Graph has a leveled planar embedding if there exists a level assignment function that maps each to one of levels, and a straight-line planar drawing of such that each vertex has y-coordinate and all edges are proper, i.e., for all we have . The latter property allows us to express the drawing as a collection of total orders , one for each level , that specifies the left-to-right order of the vertices on level [36]. For each level , let be the rightmost vertex on level in such that we have for some with , or if there is no such vertex, let be the leftmost vertex on level . Arched leveled planar embeddings extend leveled planar embeddings by also allowing non-monotone arching edges between the leftmost vertex on level and vertices with and [34]. These edges can be drawn crossing-free below the lowest level; see Figure 7b. The problem Arched Leveled Planarity asks whether has a level assignment that admits an arched leveled planar embedding. Heath and Rosenberg [34] showed that the spine order of a one-page queue layout of a graph induces a level assignment together with a vertex order on each level that together yield an arched leveled planar embedding of and vice versa; see Figure 7.
We show that, when seeking a one-page queue layout of , one can branch over the information needed to infer the level assignment for a corresponding arched leveled planar embedding. Consider an arbitrary orientation of the edge set as an oriented arc set and let be a function that determines if an arc should be ordinary () or arching ( ). The tuple is called a labeling of ; see also Figure 7c. A level assignment is said to be consistent with if and only if, for every , it holds if and if . Similarly, an embedding is consistent with if its level assignment is consistent and we have for every . Clearly, every arched leveled planar embedding of induces a labeling that is consistent with . Conversely, we can reobtain from this by fixing an arbitrary vertex to level 0, performing a BFS from using the direction information in to determine levels for all other vertices above and below, and potentially shifting all assigned levels such that their numbers span the same range as those in . This is formalized by the following lemma.
Lemma 26 (★).
Let be a labeling of . In linear time we can compute a level assignment that is consistent with the labeling or report that no such assignment exists. If there exists an arched leveled planar embedding that induces , then there also exists one that induces and uses the level assignment .
To now decide if a given graph has an arched leveled planar embedding , we can branch over all different labelings of . In each branch, we use Lemma 26 to compute a level assignment or immediately reject the branch. Thus, it remains to check in each branch, i.e., for each level assignment, if admits a corresponding arched leveled planar embedding. We do so using a linear-time reduction to the problem Level Planarity, which requires a level assignment as part of its input but does not allow arching edges. We emulate arching edges in Level Planarity as follows (see also Figure 8). First, we enclose the whole graph in a frame, which is a cycle spanning from below its lowest level to above its highest that will have a unique embedding (up to reflection) and for which we ensure that the remaining graph is drawn inside of it. Between each pair of levels , we add a level and subdivide all edges to ensure properness. We use and to refer to the two vertices of the frame cycle that are on level . Replace each arching arc with on level with the edges , , and to ; see Figure 8. Observe that this forces to become the leftmost vertex on level and to be right of any vertex adjacent to one on level . We provide a formal construction and show equivalence in the full version [14]. Using the known algorithm for testing Level Planarity in linear time [35, 36], we finally obtain our third contribution.
Theorem 3 (★). [Restated, see original statement.]
Given an -vertex graph , we can compute a -page queue layout of (if one exists) in time .
6 Concluding Remarks
While our results improve the state of the art on computing linear layouts in several directions, they also highlight the prominent open questions in this area. In particular, Theorem 1 moves us closer to settling the long-standing open questions of whether treewidth or treedepth can be used to facilitate the computation of linear layouts [21, 7, 25, 8, 26]. At the same time, Theorems 2 and 3 yield the question of whether these classical problems can be solved in single-exponential time.
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