Schedule-Based Attack Against TSN TAS with Frame Preemption

The effective transmission time over a TAS cycle equals the cycle duration $t$, i.e., ${\sum }_{i=0}^{|Q|-1}{d}_i=t$ when gate intervals do not overlap, where $d_i$ denotes the interval during which a specific queue $q_i$ can transmit based on the GCL, assuming a single transmission window per queue per cycle. When multiple gates overlap, only one transmission occurs and the overlapping interval is counted once toward $t$. To estimate $d_i$, for each $q_i$, observer frames are sent at time $T_{i,j}=T_0+j\cdot \tau$, where $T_0$ is the offset, $\tau$ represents the transmission interval, and $j=0\mathrm{\dots }N-1$ is the index of frames sent to $q_i$. These frames are sent periodically to measure their end-to-end delay $L_{i,j}$. The absolute residual delay ${\delta }_{r_{i,j}}$ represents the waiting time at the switch egress queue prior to transmission. If $L_{i,j}$ is measured over a single hop from the switch egress to the receiver, ${\delta }_{r_{i,j}}$ is given by:

where ${\delta }_{\text{prop}}$ and ${\delta }_{\text{proc}}$ denote the propagation and processing delays.

${\delta }_{r_i,j}$ may include the preemption delay due to interruption by a higher-priority eMAC frame. However, because preemption events occur dynamically at runtime, it is difficult to determine whether and when a frame was preempted solely from the observed delay. Blocking by frames of the same priority is considered a queuing delay. According to IEEE 802.3br, frames smaller than 123 bytes cannot be preempted. Setting the observer frame size below 123 bytes ensures ${\delta }_{r_{i,j}}$ only reflects time spent in the queue, excluding preemption delays. Frames experience minimal queuing delay when the gate is open and increased delay when the gate is closed. Increased queuing delay may also occur under heavy traffic load, but such variation is not fixed, whereas delays due to gate closures exhibit periodic patterns across cycles.

To detect gate behavior, residual times are grouped into windows per queue, where each window contains consecutive frames with similar queuing delay, corresponding to the same gate opening. Similarity is determined using a threshold $T_{\text{diff},i}$. $T_{\text{diff},i}={\mu }_{\{\mathrm{\Delta }{\delta }_{r_i,j}\}}+{\sigma }_{\{\mathrm{\Delta }{\delta }_{r_i,j}\}}$:

where ${\mu }_{\{\mathrm{\Delta }{\delta }_{r_i,j}\}}$ and ${\sigma }_{\{\mathrm{\Delta }{\delta }_{r_i,j}\}}$ denote the average successive difference of ${\delta }_{r_i,j}$ and its deviation, respectively. Once $T_{\text{diff},i}$ is known, the time windows can be formed: the attacker initializes the time window using the first observer frame’s residual delay ${\delta }_{r_i,0}$ as $W_{i,k}=\{{\delta }_{r_i,0}\}$ where $k$ is the index of the current window being formed. Subsequent frames are added to the current window if the difference between consecutive residual delays is not above $T_{\text{diff},i}$.

When the difference between two consecutive residual delays exceeds the threshold, it indicates a possible gate closure event or a significant change in traffic conditions. A new window $W_{i,k+1}$ for $q_i$ is then created. As a result, $T_{\text{diff},i}$ accounts for the observed ${\delta }_{r_i,j}$ variability. The value segments the windows and differentiates gate closures from normal traffic variations.

As time windows are formed for each queue, they are stored in $𝒲[(i,k)]$, representing the observed transmission window for queue $q_i$ at index $k$. For each window, the earliest and latest observed departures are then identified as $T_{\min ,i,k}$ and $T_{\max ,i,k}$, respectively.

We note that the attacker does not need to hit the exact moment a gate opens again after a cycle. They only need to time their frame within a range close enough to ensure the frames can transmit during the targeted slot and can be preempted by an express frame.

By computing the differences $\mathrm{\Delta }{T}_{\min ,i,k}=T_{\min ,i,k+1}-T_{\min ,i,k}$ and $\mathrm{\Delta }{T}_{\max ,i,k}=T_{\max ,i,k+1}-T_{\max ,i,k}$, we capture the range of possible cycle durations. Since the difference between consecutive minimum values, $\mathrm{\Delta }{T}_{\min ,i,k}$, can sometimes be larger than the difference between maximum values, $\mathrm{\Delta }{T}_{\max ,i,k}$, depending on the observed data, we compare both values in the $t$ range. This ensures that we correctly identify the smallest ($t_{\min }$) and largest ($t_{\max }$) observed intervals, providing an estimation of the minimum and maximum possible cycle durations. The minimum interval reflects the shortest recurring cycle period, while the maximum interval accounts for potential variations due to network conditions and bounds the cycle time range. We then select the estimated minimum and maximum cycle time across the available queues:

The gate duration is then calculated as the difference between the maximum and minimum delays observed within each window $W_{i,k}$. The transmission time of the last frame is added to account for transmission within the open slot. To determine the maximum gate duration observed across the cycles, the largest value across all windows is selected:

We identify two main causes of overestimation, firstly due to the remaining transmission time after the gate closes. While $d_i$ is bounded by the configured gate open slot, any frame arriving after the gate closes cannot be transmitted until the next cycle. Although the observer frames are too small to be preempted, if one of them is still transmitting when the gate closes, its remaining transmission time contributes to the observed delay and is added to the gate duration estimate. This addition is expected to have minimal impact. Secondly, when multiple queues share a common slot, observer frame delays may overlap within the same estimation window, and multiple queues may be assigned to the same gate-open window. Let $q_m$ denote another queue that potentially shares the same gate schedule as $q_i$. We verify this by comparing their estimated gate-close times. If $|{\delta }_i-{\delta }_m|\le T_{\mathrm{diff},i}$, then $q_i$ and $q_m$ are inferred to share the same gate window in cycle $k$, and their observations are merged into a single window, $W_k=W_{i,k}\cup W_{m,k}$. Note that $T_{\mathrm{diff},i}$ is computed only when ${\delta }_{r_i}$ contains more than two values; otherwise, the corresponding queues are grouped within the same window.

Algorithm 1 estimates a cycle time range $[t_{min},t_{max}]$ and $d_i$ for each $q_i$ probed by the attacker. Each $O_{\iota }$ are sent at time $T_{i,j}$ and is used the compute ${\delta }_{r_i,j}$ (Lines 6 and 7). All residual delays collected for $q_i$ are then recorded as ${\delta }_{r_i}$ (Line 8). Next, the time elapsed between pairs of consecutive ${\delta }_{r_i,j}$ is computed to establish the threshold value $T_{\text{diff},i}$ in Line 11. Using $T_{\text{diff},i}$, residual delays are grouped as transmissions that potentially occur within the same cycle $k$ as $W_{i,k}$ in Line 12. On Line 14, the window set of $q_i$ is stored in $𝒲$, where each $W_{i,k}\in 𝒲$ represents an observed transmission window for $k=0,\mathrm{\dots },𝒦$. The expressions $T_{\min ,i,k}$ and $T_{\max ,i,k}$ on Lines 17 represent the earliest and latest observed departure times within a given window $W_{i,k}$ from a queue, respectively. These values are used to estimate the duration of the gate opening $d_i$, and the range of possible cycle durations $\mathrm{\Delta }{T}_{\min ,i,k}$ and $\mathrm{\Delta }{T}_{\max ,i,k}$ (Lines 20 and 21) for each queue. Finally, $t_{min}$ and $t_{max}$ are computed on Lines 22 and 23 respectively.

Using the software simulator we generated 10,000 simulation runs lasting approximately 5 minutes of simulated time. In each run, the number of queues was randomized between 3–8, with a fixed link speed of 100 Mbps. The cycle time was randomly chosen from [3,000,15,000], and gate durations were assigned via a weighted random distribution. Two types of traffic were modeled per queue: observer frames below 123 bytes were generated periodically at 300$\mu s$ intervals to probe the gate-opening patterns. Additional background frames with randomized sizes from 123-1500 bytes were also generated to simulate normal network load, to be between $50-85\%$ load ratio compared to observer frames. These background frames shared the same transmission queues. To model preemption in the simulation, the number of express queues is set to at least 33$\%$ of the total number of queues, rounded up to the nearest whole number. When an express queue is transmitting, the gates of other queues remain closed. However, preemptable frames may still be partially transmitted if their gates were previously open.

Using Algorithm 1 and the refinement analysis, we analyzed the observer frames delays to obtain the transmission windows, the cycle time range and gate durations. During refinement, observer frames were aligned with the estimated cycle time to improve gate duration accuracy. For each simulation run, the estimated cycle time was compared against the true cycle time. Estimation accuracy was computed as $\left(1-\frac{|\text{Estimated}-\text{Actual}|}{\text{Actual}}\right)$. Figure 6(a) shows the actual cycle time in blue (i.e., 100% accuracy) and the estimated cycle time in green. Our approach achieves over 99$\%$ accuracy in most cases, with the lowest observed accuracy of about $94\%$. The average accuracy is $99.74\%$.

To evaluate gate observability and window segmentation, we generated periodic ICMP observer traffic (assigned to priority 2) from an LS1021ATSN host to an LS1028-2 receiver through a TAS-configured switch. All egress queues were defined in the GCL, but only the ICMP queue was allowed to transmit during its gate window. The TAS cycle time was fixed at $1\mathrm{ms}$, and the ICMP gate allocation was swept across nine configurations ranging from $[900\mu s,100\mu s]$ to $[100\mu s,900\mu s]$ open/closed durations. ICMP packets were sent every $50\mu s$, and end-to-end delays were extracted from PCAP traces. Algorithm 1 was applied to segment windows $W_{q_i,k}$ and infer window start times. Figure 6(b) shows the inferred window boundaries and estimated cycle times. When the open window is short (Configs 1–7), window boundaries are stable, with $T_{s,q_i,k-1}\in [0.30,0.40]$ ms and $T_{s,q_i,k}\in [1.20,1.40]$ ms, clearly revealing the $1\mathrm{ms}$ cycle. As the open window increases (Configs 8–9, $\ge 80\%$ open), temporal contrast decreases, leading to less stable segmentation and a reduced cycle estimate ($0.50$–$0.55$ ms). This confirms that segmentation is most reliable when closed intervals provide strong temporal separation or when multiple queues are observed.

Table 5 summarizes the TSN flow configuration used in this case study, which is inspired by [18]. The objective is to evaluate the impact of a compromised I/O device that intentionally aligns its transmissions with TAS gate boundaries to induce adversarial blocking. Two BBB devices serve as the controller and I/O Device 1 (IOD1), respectively. An LS1021A device acts as I/O Device 2 (IOD2) and is assumed to be compromised. All traffic is forwarded through a TSN switch (LS1028-1) toward a receiving switch (LS1028-2), which supports frame preemption. The controller and IOD1 generate express traffic mapped to queues 7 and 6, respectively. In addition, IOD1 generates an independent AVB flow mapped to queue 5, which serves as the victim flow $f_v$, while IOD2 generates BE traffic mapped to queue 2-0; both flows are configured as preemptable traffic.

TAS is enabled on interface swp1 of LS1028-1 with a three-entry GCL and a cycle time of 400 $\mu$s. Queues 7, 6, and 5 are each allocated 50 $\mu$s, while queues 0–2 share a 250 $\mu$s window. All bridge ports are synchronized via PTP. Using crafted ICMP observer frames, we inferred gate timing and measured end-to-end delay. The measured propagation delay was approximately 35 ns. Gate closures of up to 148 $\mu$s were observed during queue transitions, and RTTs converged to approximately 252 $\mu$s, confirming the expected 400 $\mu$s cycle. Frames larger than twice the MIN-FRAG-SIZE (60 bytes) exhibited fragmentation effects, verifying that queues 2 and 5 were preemptable. For the SBA, the compromised node aligns its transmissions with the end of its assigned gate window (${\rho }_{\iota ,j}=2$). Release times are computed using the inferred window boundaries and cycle time as defined in Algorithm 2. Using the GCL base time $T_b$, the current TAS cycle index is computed as $k=\lfloor \frac{T_{\text{curr}}-T_b}{t}\rfloor$. IOD2 transmits with a period approximately $800\mu s$ with an offset $ϵ=5\mu s$, aligning near gate boundaries to increase preemption events.

PCAP traces were collected over a five-minute interval. Under normal operation, the average delay of $f_v$ remained near 150 $\mu$s with no deadline violations (Figure 7(a)). Under SBA, approximately 448,800 preemption events were observed, reflected by a sharp increase in the MACMergeFragCountTx counter. Under our configuration on the switch, the resumption of preempted pMAC frames results in spillover. Analysis of 100,000 victim frames (averaged over bursts of 100) showed that roughly 10% of the first 60 bursts violated deadlines, with delays peaking at 365 $\mu$s. This behavior indicates that, in some cycles, $f_a$ was itself preempted. However, when sufficient transmission time remained within the victim’s gate window, these events did not consistently result in deadline violations for $f_v$. As preemption accumulated, worst-case delays increased sharply, reaching 11.8 ms. Beyond the 78th burst, persistent deadline misses caused frame drops, with delivery falling below 80%. For comparison, we evaluated a flooding attack without GCL awareness, transmitting frames every 105 $\mu$s (approximately $9,500$ packets/s). Victim frames initially met deadlines, but delays increased rapidly due to excessive queuing, reaching 31.3 ms by the 22nd burst, after which sustained frame loss was observed (Figure 7(b)).

All configurations employ a fixed gate duration equal to one-third of the cycle across all queues. Configuration (a) represents a generic traffic scenario in which all flows generate the same traffic type. The flow with ${\rho }_{\iota ,j}=6$ is mapped to an eMAC queue, while the remaining flows are assigned to pMAC queues. The attacker generates pMAC traffic with ${\rho }_{\iota ,j}=4$. All traffic classes are configured with short $d_i=15\mu s$, with a total cycle time of $45\mu s$ [25]. Configuration (b) represents a tactile control scenario in which the flow with ${\rho }_{\iota ,j}=6$ is mapped to an eMAC queue, while the remaining flows are AVB traffic mapped to pMAC queues. Larger $d_i=200\mu s$ with longer periods are used to emulate multimedia traffic.

Under configuration (a), uniformly short gate durations result in frequent preemption events affecting both victim and attacker frames. Although the attacker’s frames are preempted, the victim’s fragment also repeatedly defers the attacker’s transmissions. This repeated preemption disrupts the attacker’s alignment with the victim gate, causing attacker fragments to be shifted outside the victim transmission window. Consequently, worst-case blocking does not occur immediately. In our measurements, a pronounced delay event occurs around the $80$th burst, where the victim experiences delays of up to $800\mu s$ due to accumulated cycle misses, as shown in Figure 8(a). This result shows that once alignment occurs, feasibility is governed by the resulting spillover overlap $E$, which captures how much attacker transmission extends into the victim window rather than by the period. However, the period sets the available deadline margin.

In configuration (b), the victim flow has a period and deadline = 24ms. While the $d_i$ of the victim remains fixed at one third of the cycle, increasing $d_v$ enlarges the victim’s transmission opportunities $d_v-E$. Consequently, the additional waiting induced by the attack, $\left(\lceil \frac{B_v}{d_v-E}\rceil -1\right)t$, remains within the available deadline margin. Figure 8(b) shows the worst-case scenario for the attacker: long gate durations absorb spillover effects, allowing the victim (Audio VBR (pMAC)) flow with $D_v$ of 24 ms to transmit within its slot despite the SBA, as the maximum delay (450$\mu$s) is not enough to cause deadline miss. Together, configurations (a) and (b) show that SBA effectiveness is governed by the interaction between the spillover overlap $E$ and the effective service window $d_v-E$ relative to the period or deadline. While varying the transmission period influences alignment and delay tolerance, it does not alter spillover formation itself once it occurs. The same overlap may therefore cause deadline violations under short deadlines, whereas under longer deadlines it can be absorbed. This motivates our subsequent evaluation of the feasibility of victim slot completion in a cycle across varying gate durations and frame sizes, while ensuring that both the gates and the periods align, allowing attacker traffic to overlap with the victim flow.

To analyze the overall effectiveness of the SBA under alignment, we next generalize beyond the single traces by analyzing the structural vulnerability of TAS schedules to SBA-induced spillover through a simulated dataset. We consider $t=500\mu s$ and parameterize the victim gate duration as a fraction of the $t$ such that $\gamma =\frac{d_v}{t}$. The observed behavior is driven by the absolute duration of the victim gate due to the fixed $t$. The attacker frame size is fixed to $1500$, and the period is fixed to one injection each cycle on average to align with the victim’s gate. We vary the victim frame size $\in \{200,500,1000,1500\}$ to control the extent to which its flow utilizes its allocated gate duration $d_v$. In Figure 9(a), the y-axis also shows the normalized overlap ratio $\frac{E}{d_v}$, i.e., the fraction of the victim $d_v$ consumed by attacker transmission and preemption overhead. A value of $\frac{E}{d_v}=1$ indicates complete overlap of the victim gate ($d_v-E=0$), whereas $\frac{E}{d_v}=0$ denotes no overlap. For small $\gamma$ (up to approximately $0.2$), the overlap reaches $\frac{E}{d_v}=1$, fully occupying the victim gate slot. As $\gamma$ increases, the victim gate duration grows faster than the attacker spillover, resulting in a monotonic decrease in the normalized overlap $\frac{E}{d_v}$. The overlap drops below one (e.g., $\frac{E}{d_v}=0.9$ at $\gamma =0.25$) and falls below one-half at $\gamma =0.60$. These results show that when the victim flows have more transmission opportunities, attacker spillover can be absorbed.

We next show how attacker overlap affects slot completion feasibility within a cycle, as illustrated in Figure 9(b). The y-axis indicates in-cycle feasibility: $1$ indicates that the victim frame completes entirely within its slot, and $0$ denotes insufficient remaining time under SBA. Since only $d_v-E$ remains usable, feasibility requires $d_v-E\ge C_v$ (Eq. 10). As $\gamma$ increases, a sharp transition to feasibility occurs once the remaining open time exceeds the victim transmission demand. For example, feasibility is restored at $\gamma =0.28$ ($d_v=140\mu$s) for a $200$ bytes frame, whereas a 1500 bytes requires nearly half of the cycle to transmit fully.