From Timing Budgets to WCETs: Robust SIL- and BSW-Aware Clustering and Allocation for Iterative Automotive Software Development
Abstract
Automotive ECUs integrate thousands of AUTOSAR runnables, substantial Basic Software (BSW), and heterogeneous multicore hardware. In iterative software-defined vehicle development, engineers must repeatedly revisit designs while maintaining stable runnable clustering and core allocations, which are expensive structural decisions. Beyond timing, Safety Integrity Levels (SILs), BSW overheads, and per-core memory strongly constrain these decisions, yet are rarely modeled jointly. This paper addresses these challenges through a chain-based analysis model that treats SIL constraints and BSW costs as first-class citizens, as well as an integrated toolchain that constructs job-level data-age constraints, forms SIL-compliant clusters, synthesizes multirate tasks, and maps application and BSW tasks to heterogeneous multicore platforms while checking timing and memory feasibility.
A case study based on a real-world motion/drive controller from our industrial partner is described, which serves as the basis for our evaluation. The evaluations are conducted using synthetic systems that reflect the characteristics of the case study. Across 13,825 synthesized systems, SIL/BSW-aware clustering substantially reduces pessimism in analysis. In the industrial configuration, our approach yields a 7% decrease in utilization, demonstrating its practical value. A refinement study, which progressively replaces early budget assumptions with WCET samples, indicates that SIL/BSW-aware clustering preserves structural decisions better than less-informed variants under the same resampling setup.
Keywords and phrases:
cause-effect chains, end-to-end latency constraints, automotive software, SIL, ASIL, AUTOSAR BSW, WCET refinement, timing analysisFunding:
Matthias Becker: The work was partially supported by the Swedish Research Council (VR) under the project nr. 2023-04773, and by Sweden’s Innovation Agency via the NFFP8 project 2024-01267: PARTI.Copyright and License:
2012 ACM Subject Classification:
Computer systems organization Real-time systems ; Computer systems organization Embedded software ; Software and its engineering Software safetyAcknowledgements:
We thank our industrial partners in the CARIAD SE, Germany, for its collaboration and constructive feedback, which improved the quality and practical relevance of this project. Generative AI tools were used to support language polishing and LaTeX formatting. The authors reviewed and edited all affected text and metadata and take full responsibility for the content.Editor:
Angeliki KritikakouSeries and Publisher:
Leibniz International Proceedings in Informatics, Schloss Dagstuhl – Leibniz-Zentrum für Informatik
1 Introduction
Automotive E/E systems continue to grow in complexity, while the industry is moving towards software-defined vehicles (SDV) with mixed-criticality functionality and frequent integration and update cycles. In such settings, architectural decisions are not made once and for all, but are revisited repeatedly as functions evolve, suppliers deliver incremental changes, and timing and memory characteristics are refined. Our goal is to keep expensive architectural decisions stable while refining budgets and incorporating feedback from timing analysis and measurement. A dominant architectural pattern is cause–and–effect chains (i. e., data flow from sensors to actuators via tasks that may run at different rates [35]), for which end-to-end timing must be met to uphold data age and quality constraints [21]. While chain-aware timing analysis and allocation are well studied, our collaboration with industry indicates that two additional drivers are often decisive for feasibility and cost, yet are underrepresented in chain-centric optimization: (i) safety integrity constraints that restrict colocation and resource sharing, and (ii) Basic Software (BSW) costs, including both task-local overheads (e. g., per-task service extensions) and global BSW tasks (e. g., providing communication and diagnosis) competing for CPU and memory. Crucially, these costs are strongly coupled to structural design choices such as how software components are clustered into tasks, how chains are decomposed, and how tasks and BSW are co-allocated to CPU cores and memory domains. This coupling makes structural changes costly: reorganizing clusters, chain partitions, and core assignments affects integration, configuration, safety arguments, and deployment effort. In contrast, timing budgets and WCET estimates are commonly refined as more implementation evidence becomes available. We therefore target a recurring architectural-analysis setting in which tighter WCET estimates progressively replace conservative budgets (required for early safety assurance). The objective is not to guarantee invariant architectures, but to reduce avoidable remapping by making SIL and BSW constraints explicit during clustering and allocation.
1.1 Problem Statement
Given (1) runnables and their chain structure with end-to-end/data-age constraints, (2) SIL labels and separation requirements for application and BSW, (3) a target multicore platform with core classes and per-core memory limits, and (4) an empirically grounded BSW cost model distinguishing global stacks and task-local overheads, compute (a) a SIL-compliant clustering of runnables into application tasks (including multirate task construction), (b) a placement of application tasks and required BSW tasks to cores/memory, and (c) a sound feasibility assessment w.r.t. timing, memory, and safety constraints under the stated modeling assumptions. We strive to provide engineers with a single integrated architectural timing-analysis toolchain that can be applied throughout iterative SDV development: given an evolving architectural model, it jointly constructs tasks, accounts for BSW extensions and global BSW tasks, and checks timing and memory feasibility under SIL and data-age constraints. A key practical challenge is that the global BSW task set is largely unknown early on; we therefore approximate its impact via a conservative envelope so feasibility analysis remains possible from the first iterations. Thus, our goal is to reduce avoidable pessimism in timing analysis by exploiting SIL/BSW knowledge during clustering and mapping, and additionally to minimize unnecessary changes to expensive structural decisions (clusters and core assignments) as timing inputs are refined from conservative budgets to WCETs.
1.2 Contribution and Outline
-
1.
Industrial case study and benchmark synthesis. We empirically characterize the interplay of SIL constraints, BSW, and memory in a production-grade motion/drive controller and derive profiles that enable realistic synthetic benchmark generation. The companion case study [15] and the Driverator benchmark generator [14] are provided as supplemental material.
-
2.
An analysis model with SIL/BSW as first-class citizens. We formalize a chain-based model that integrates (i) SIL constraints spanning application and BSW, (ii) explicit BSW accounting that distinguishes task-local overheads from global platform services, and (iii) per-core memory limits. To reflect the mixed-criticality practice observed with our partners, we also allow a mode-dependent chain structure. Our model integrates feasibility-preserving estimates for parameters that are still unknown but supports sound analysis when worst-case bounds are available.
-
3.
Integrated analysis/optimization toolchain and empirical validation. We implement a full toolchain that combines job-level dependency construction for data-age constraints, SIL-constrained clustering, multirate task construction, and BSW- and memory-aware mapping to heterogeneous multicore platforms. Using thousands of synthesized systems grounded in the case study profiles, we quantify the impact of BSW overheads and show that SIL/BSW-aware clustering can substantially reduce analysis pessimism compared to less informed variants; additionally, we report that resulting clusterings/mappings are more stable than less informed variants when conservative budgets are refined towards WCET inputs.
2 Related Work
End-to-end semantics in automotive.
The mapping and scheduling of automotive applications have been extensively studied. Kramer et al. [35] characterize an engine management system and highlight the complexity of cause-effect chains (CECs) [1]. Feiertag et al. [21] classify end-to-end delay semantics for such chains, and the WATERS Industrial Challenge 2017 [28] examines communication semantics on multicore platforms.
Communication and precedence modeling.
Timing-analysis tools provide end-to-end latency checks for multi-rate CECs [29, 30, 48], typically assuming detailed system information. The Logical Execution Time (LET) paradigm decouples communication from execution and eases integration on multicore platforms [27], but can increase end-to-end latencies compared to implicit communication [6, 39, 47]. Ernst et al. [20] and Gemlau et al. [25] discuss extensions of LET to distributed settings, and several optimization strategies mitigate LET-related latency penalties [37, 50, 26]. Complementarily, precedence-based models capture multi-rate dependencies explicitly: Forget et al. [22] introduce a synchronous data-flow language and propose fixed-priority scheduling without synchronization to realize extended precedence constraints [23]. Becker et al. [5, 7] compute end-to-end latencies via job-level dependencies (JLDs), which Klaus et al. integrate into table-driven scheduling [34] and later into dynamic scheduling via system transformations [33]. Dietrich et al. [16] derive global control flows for whole-system WCET analysis, extended to fuzzing-based dynamic whole-system timing analysis by Berger et al. [8].
Runnable-to-task construction and clustering.
Several works examine how the runnable/task structure affects schedulability and analysis. Monot et al. [43] bundle related runnables into sequencer tasks on multicore platforms. Khenfri et al. [32] investigate runnable-to-task allocation based on the multiframe task model [42], and Becker et al. [4] similarly merge tasks under JLD constraints. These approaches motivate treating task construction as a first-class design dimension rather than a fixed input.
Allocation and design flexibility.
A broad body of work addresses constrained task-to-processor allocation, often coupled with priority assignment and schedulability analysis [12, 13, 38]. In the automotive context, Zheng et al. [51] and follow-up work (e. g., [52, 11]) optimize allocation/priority choices under end-to-end constraints for distributed architectures. Beyond optimizing a single design point, flexibility- and change-aware allocation has been studied using scenario-based evaluation and robustness objectives, aiming to accommodate future changes with minimal alterations to an existing mapping [3, 19]. Tool-supported generation flows have also been explored for time-triggered multicore systems [24]. Bhat et al. [9] further demonstrate allocation techniques under additional practical constraints in embedded automotive systems. Exact formulations based on (mixed) integer linear programming have also been proposed for constrained mapping and priority assignment problems [17, 44, 49, 51]; however, these approaches typically assume a given task set and cost model.
Mixed criticality and safety constraints.
Functional safety standards such as ISO 26262 [31] mandate freedom from interference across criticality levels, underscoring the need for SIL-aware allocation and scheduling. Mixed-criticality scheduling [10] represents a natural candidate to combine strong partitioning with efficient resource sharing and is, for example, part of Eclipse’s SDV framework. Recent work also considers precedence constraints, for example, Socci et al. [46, 45] for precedence-constrained mixed-critical jobs on multiprocessors and Medina et al. [41, 40] for (multi-periodic) mixed-criticality DAG models with mode-dependent static schedules. In principle, such precedence/DAG formalisms could encode parts of SIL/BSW-induced ordering or mode-dependent functionality.
State-of-the-art Gap.
Prior work advances cause–effect-chain semantics, precedence modeling, clustering, and allocation. Yet these lines are rarely integrated with (i) SIL-constrained clustering and (ii) an explicit BSW cost model that distinguishes task-local overheads from global platform services and captures their CPU/memory impact. As a result, current approaches either abstract away from BSW and safety-induced separation, which can introduce unnecessary pessimism and obscure the true feasibility and cost trade-offs that practitioners face. Moreover, most allocation techniques assume fixed constraints and task sets, whereas in our setting task construction (i. e., runnable mapping), SIL feasibility, and BSW overheads are coupled: clustering decisions change the task set and directly affect BSW overhead and memory aggregation. This coupling motivates our integrated chain-aware flow that treats SIL and BSW as first-class citizens while remaining compatible with iterative refinement in SDV development.
3 System Model
This section introduces our system model, focusing on information typically available in early design and its relation to implementation-level artifacts.
Safety Integrity Levels.
We use the ASIL levels of ISO 26262 [31], ranging from QM (Quality Management, i.e., functionality without an ASIL assignment) to ASIL D, the highest integrity level considered here. We abstract ASIL as a safety integrity level (SIL) and denote the finite set of supported levels by .
Application Layer.
Runnables are the elementary units of execution; we consider a set that communicates via AUTOSAR implicit communication [2]. At design time, runnable is characterized by an execution-time (depending on the development phase given either as abstract budget or sound upper bound/WCET) and a period .
For allocation, runnables are grouped into software components (SW-Cs) . Each SW-C contains a runnable subset and has a SIL that is inherited by its runnables: . Its memory requirements are and , hence .
Cause-effect chains capture functional dependencies. Each chain is modeled as a DAG over runnables and is subject to a maximum data-age bound . In mixed-criticality settings, a chain may include QM functionality that is replaced by a substitute in safe mode. We denote such a substitute by : it provides a high-assurance replacement for a QM runnable that is active only in safe mode, while the original QM functionality is used only in regular mode. The notation is descriptive rather than a new ASIL level: it marks ASIL-constrained substitute functionality for a QM runnable. We model this as an additional runnable with mutually exclusive activation semantics; details are given in Sec. 4.2.
Platform and Scheduling.
We consider a platform’s lockstep cores used for high-SIL workloads, modeled as , where provides capacities and . We assume WCETs to be upper bounds including potential inter-core interference. Consequently, when using early-stage budgets, the result is a conditional architecture-level feasibility assessment that becomes sound once budgets are refined to actual WCETs.
We assume partitioned, preemptive fixed-priority scheduling. Runnables are allocated to periodic tasks (which may execute multiple runnables), and each task is statically mapped to a core and assigned a fixed priority. The specific allocation strategy of different runnable types to tasks, and the determination of task parameters is discussed in Section 4.
Task-local BSW extensions account for service overheads attached to application-task activations, such as RTE interaction, communication handling, mode management, and OS/RTE glue code. We model this overhead by a factor depending on the number of runnable instances in a task frame, yielding an execution-time extension for task . The factor is not a communication-edge model but an empirical task-composition proxy.
Global BSW tasks implement central system services (e.g., OS, communication, diagnostics) and are modeled as periodic tasks comprising up to 200 runnables each, with parameters . Their aggregated ROM footprint on core is captured by , reducing the available capacity . In early phases, the number and parameters of global BSW tasks are often unknown; we therefore estimate their impact via a conservative utilization/memory envelope (Sec. 4.4).
Requirements.
- R1
-
Each runnable is assigned to exactly one periodic task with implicit deadlines; a task may contain multiple runnables. Tasks are mapped under partitioned FP scheduling.
- R2
-
Clustering/merging must preserve SIL separation and chain context and must respect data-age constraints (modeled later as JLDs).
- R3
-
All runnables of the same SW-C must be co-located on one core; per-core ROM/RAM capacities must not be exceeded.
- R4
-
BSW overheads are modeled as task-local extensions (via ) and as global BSW tasks with per-core memory envelopes.
4 Automotive System Analysis Across Iterative Development Phases
This Section introduces our approach for the iterative development of automotive systems. It consists of the following five main phases, which are also visualized in Figure 1:
-
1.
Deriving job-level dependencies. We compute Job-Level Dependencies (JLDs) from the cause–effect chains and their data-age constraints, as described by Becker et al. [5]. These JLDs capture the ordering constraints required to satisfy data-age bounds and form the temporal backbone of our construction (Section 4.1).
-
2.
Building SIL-aware runnable clusters. We group runnables of chains into clusters based on safety-criticality, ensuring they share the same SIL and periods. This prepares them for later merging while preserving SIL and chain semantics (Section 4.2).
-
3.
Creating application tasks with BSW extensions. Each safety-critical cluster is transformed into a multiframe application task using the Arbitrary Periodic Solution (APS) [32, 4] method, which combines different periods within a single task. Budgets include runnable WCETs and frame-local BSW extensions (Section 4.3).
-
4.
Estimating global BSW impact. Based on the task-local BSW extensions, we approximate, if necessary, the remaining global BSW tasks (utilization and memory footprint) using utilization bounds and platform parameters (Section 4.4).
-
5.
Composing task groups and mapping to cores. JLDs and SW-C boundaries are used to create task groups that must reside on the same core. All application and BSW tasks are then allocated to cores using a worst-fit heuristic. Per-core schedulability and memory constraints are checked in tandem (Sections 4.5 and 4.6).
Overall, our toolchain takes an architectural model and WCETs (or budgets, depending on the development phase) and returns a schedulability- and memory-validated core mapping, along with the induced task decomposition (tasks, clusters, and remaining precedences). Each step consumes the artifacts of the previous step and produces the next engineering artifact: data-age dependencies, SIL-compatible runnable clusters, multiframe application tasks with local BSW extensions, an estimated global BSW envelope, coherent task groups, and finally a schedulability- and memory-validated core mapping.
Conventions.
All symbols and index conventions in this Section are summarized in Table 1. In particular, SW-Cs are indexed by , runnables by (with instances/jobs indexed by ), chains by , clusters by , tasks by , global BSW tasks by , task groups by , cores by , and frames within multiframe tasks by .
| Symbol | Description | Symbol | Description |
|---|---|---|---|
| CPU core of core set | set of cause-effect chains | ||
| number of cores | cause-effect chain | ||
| ROM/RAM capacity of | data-age bound of | ||
| SW-C of SW-C set | chains containing | ||
| SIL of | set of runnable-level JLDs | ||
| ROM/RAM budget of | JLD: inst. of prec. inst. of | ||
| set of runnables (on ) | hyperperiod for repeating JLDs | ||
| runnable / instance of | remaining task-level JLDs | ||
| SIL inherited by | set of task groups | ||
| WCET/period of | task group (must be co-located) | ||
| task of periodic task set | remaining independent tasks | ||
| number of tasks | set of SIL-aware clusters | ||
| fixed priority of task | SIL-aware cluster | ||
| set of multiframe app. tasks | set of runnable instances in a cluster | ||
| multiframe application task | set of instance-level dependencies | ||
| SIL of | GCD period / major cycle / #frames | ||
| period/deadline of | frame index of instance of | ||
| set of global BSW tasks | earliest/latest feasible frame | ||
| global BSW task | position of within its frame | ||
| WCET/period of | ASW execution time of frame | ||
| SIL of | BSW extension time of frame | ||
| utilization bound for global BSW | total WCET of frame | ||
| BSW ROM footprint on core | predecessors of instance in | ||
| set of task-local BSW extensions | external predecessor (outside cluster) | ||
| BSW extension attached to | external successor (outside cluster) | ||
| WCET of local BSW extension | # runnables assigned to frame | ||
| utilization of local BSW ext. | frame-wise local BSW cost factor |
4.1 Meeting Data Age Constraints by Job-Level Dependencies
Constructing tasks from application runnables is challenging when these participate in cause–effect chains with data-age constraints. We address this by transforming end-to-end data-age bounds into JLDs using the heuristic by Becker et al. [5, 7]. Their approach first identifies all propagation paths, independent of scheduling and allocation policy, and then imposes an order on instances such that only those respecting data-age constraints remain.
We apply this heuristic to all chains in and obtain a set of JLDs . A JLD states that instance of runnable must execute before instance of runnable . This constraint repeats with the hyperperiod , i. e., the least common multiple of the two periods. Satisfying all JLDs at runtime is sufficient to guarantee the original data-age constraints of all cause-effect chains. From this point, we therefore operate on instead of the original data-age constraints.
4.2 Designing Criticality-Aware Clusters for System Modes
Automotive systems typically distinguish between two operating modes: regular and safe. Safe operation is entered upon specific events and represents a temporary degradation mode in which all QM-based runnables are inactive. The concrete configuration of cause-effect chains within the application structure depends on functional and non-functional design decisions and must adhere to timing and safety requirements.
Figure 2 shows four example cause-effect chains (colored underlays) in both modes. A special case occurs in the orange chain: a QM runnable is integrated alongside SIL-constrained runnables in regular mode – it serves to improve QoS without having to be managed in accordance with SIL. In safe mode, this functionality is replaced by a high-assurance substitute runnable , which provides a simple replacement value. The XOR condition indicates that and are mutually exclusive across operating modes. Conversely, the green chain is composed solely of QM components whose comfort functionality is temporarily deactivated during safe operation.
Cluster Construction Rules.
Our goal is to construct a set of criticality-aware runnable clusters such that all runnables in a cluster share the same SIL and compatible chain and period properties. These clusters are the units transformed into application tasks in the next phase (Section 4.3). We build in three steps: (i) Per-chain grouping: for each chain , we group runnables of equal SIL into preliminary clusters. (ii) Conflict resolution: if a runnable appears in multiple preliminary clusters (chain sharing), we iteratively split/merge affected clusters until each runnable belongs to exactly one cluster while preserving identical chain context . (iii) Period-cap refinement: if a cluster contains more than two distinct periods, we keep the two most frequent periods (counted over runnable occurrences in that cluster; ties broken by choosing the shorter period) and split off remaining periods into separate clusters. The cap is not a theoretical limitation. It is an engineering heuristic: adding further periods increases the APS major cycle and the number of frames, which enlarges the CP model and often increases the maximum frame cost through sparse runnable placements. We therefore keep at most two periods per cluster to preserve schedulability margins and solver tractability. Formally, each cluster must satisfy:
| (1) |
Here, returns the set of cause-effect chains containing , and returns the number of distinct runnable periods in cluster .
Figure 2 illustrates the construction by clusters to across four chains. We first form per-chain clusters by grouping runnables of equal SIL that appear in the same chain. We then resolve conflicts where a runnable would belong to multiple clusters (e. g., due to chain sharing) by splitting or reassigning clusters until each runnable appears in exactly one cluster (e. g., and ). If a chain exhibits more than two periods for the same SIL, we assign the two most frequent periods to the same cluster and keep additional periods separate to avoid excessive utilization growth. Finally, substitute functionality within a SIL-constrained chain is treated as a separate cluster (e. g., ). The resulting set provides SIL/chain/period-consistent clusters that serve as input to the task-creation step in Section 4.3.
4.3 Creating Application Tasks from Safety-Criticality Runnable Clusters with Basic Software Extensions
Before detailing the construction of application tasks, we illustrate the successive steps in Figure 3. Figure 3(a) shows an example cause-effect chain with periods , , and . Each software component (SW-C) , , and contains one runnable , , and , respectively, and the safety integrity level (SIL) of differs from the two subsequent SW-Cs ( and ) which share the same SIL .
Figure 3(b) then shows the data propagation paths derived from the data-age constraints, as explained in Section 4.1; paths that violate the age bound are removed (dashed lines). Based on these chains and SILs, safety-criticality clusters are formed as described in Section 4.2 (Figure 3(c)). Finally, Figure 3(d) summarizes the transformation from periodic runnables to application tasks, combining timing constraints, SIL restrictions, and basic software extensions (in particular for communication services). In the following, we formalize this construction and present the heuristic used to create the corresponding application tasks.
Multi-Frame Tasks.
For each critical cluster , we create exactly one multiframe application task that inherits the cluster’s SIL. We follow the Arbitrary Periodic Solution (APS) [32, 4] method, which combines multi-periodic runnables into a single AUTOSAR-compliant multiframe task [42]. A multiframe task is a periodic task with period and deadline , whose frames have frame-specific WCETs repeating every activations. For a cluster with runnable periods , APS defines
with frames over one major cycle . Runnable executes instances per cycle. We denote the -th instance by for , and assign it to exactly one frame . Within each frame, the order of runnable instances is given by . We assume an implicit deadline for the merged task.
To go beyond [4], which focuses on multi-rate patterns and JLDs, we integrate SIL and BSW impact into the task configuration. We formulate the assignment of runnable instances to frames as a Constraint Programming (CP) problem with the objective to minimize (Eq. 10), that is, it balances frame loads to reduce worst-case utilization. All runnable instances in form the instance set
Runnable-level JLDs between runnables of are transformed into precedences between runnable instances, repeated over . For example, a JLD induces an instance-level precedence (and corresponding repetitions in subsequent cycles). We denote the resulting set of instance-level dependencies by .
CP Outcome and Failure Handling.
For each cluster we solve the CP model (and, if necessary, retry after conservative cluster refinement) to obtain (a) a frame assignment and within-frame order for all instances in , and (b) frame costs used to derive the periodic abstraction . If the CP model is infeasible (e. g., due to tight external predecessors/successors), we conservatively refine the cluster by splitting off the runnable(s) responsible for the violated bounds and retry.
Decision Variables.
The main decision variables are: (a) , the frame index of runnable instance , and (b) , the position of within its frame. For convenience, we use as an indicator that equals if is assigned to frame , and otherwise. The exclusive (application-only) execution time of frame is
| (2) |
Let denote the number of runnable instances in frame . We assign a task-local BSW extension factor based on the case-study profile: smaller frames incur larger relative BSW overhead, whereas larger frames amortize task-boundary service costs across more runnable instances. This yields the frame-local BSW extension
| (3) |
Thus, captures empirically observed task-local BSW extension ratios, not the number or topology of explicit runnable-to-runnable communication edges. The total WCET of frame is . For later schedulability analysis, we abstract the multiframe task as a single periodic task with
JLD Handling and Frame Bounds.
The execution window of runnables, when assigned to a task , is either equal to the task period or smaller. If JLDs are not considered during frame assignment, it can result in assignments that make it impossible to meet an imposed JLD. For example, if a successor runnable is allocated to a frame that must complete before the predecessor runnable is released. External predecessors/successors further restrict feasible frames (Equations 4–5).
Not all original JLDs are fully internal to the cluster; some relate runnables of different SILs and thus span multiple clusters. We capture these via helper functions: (a) returns all predecessors of in , and (b) / return predecessors / successors outside .
Release times and deadlines restrict the earliest and latest feasible frame for each runnable instance. For we derive
| (4) |
| (5) |
and enforce
| (6) |
Constraints.
To avoid overruns within one activation of the multiframe task, we require the worst-case frame time to fit into one base period:
| (7) |
Within each frame, runnable instances must have a strict order:
| (8) |
All internal precedences in must be honored by either placing predecessors in earlier frames or, if in the same frame, before their successors:
| (9) |
for all .
Objective Function.
Since later analysis uses the periodic abstraction with execution time , we balance frame loads by minimizing the worst-case frame time:
| (10) |
From runnable-level to task-level JLDs.
After solving the CP model, runnable instances are bound to frames, and frames are bound to tasks. JLDs between instances belonging to different clusters induce task-level JLDs between the corresponding multiframe tasks. A JLD between runnables mapped to different tasks is translated into a task-level JLD between these frames, repeating with the hyperperiod of the two tasks. Thus, a JLD , with mapped to and mapped to , is translated to a new JLD . We apply this translation to all cross-cluster dependencies, obtaining a reduced set of JLDs .
Finally, the created application tasks form the set , and the corresponding BSW extensions form , with . These sets, together with , are the input to the subsequent steps on global BSW impact, task grouping, and core allocation.
4.4 Determining Basic Software Impact
BSW aggregates the runtime environment, communication stacks, OS services, diagnostics, and related functionality. Its contribution to execution time and memory is substantial and depends on the task structure. We model this impact through two distinct channels.
First, task-local BSW extensions account for service work attached to application-task activation boundaries, such as RTE and communication handling. For every multiframe task , a corresponding extension contributes an execution-time extension . The frame-local factor is derived from the task-local BSW extension profile in Section 5.1. For each frame, we select the BSW-extension ratio from the range associated with its number of runnable instances and use a conservative value from that range. We additionally enforce the monotone trend observed in the case study: relative BSW overhead decreases as more runnable instances share the same task frame. Thus, is an empirical early-phase abstraction of task-local service overhead, not a communication-edge model. The cumulative utilization of all task-local extensions is
| (11) |
Here, summarizes the utilization contribution of all task-local BSW extensions, based on each extension WCET and the period of the corresponding application task.
Beyond these extensions, the system also requires dedicated global BSW tasks for system-wide operations, described by . From a BSW perspective, the total number of periodic tasks considered for the utilization envelope is
| (12) |
Since every application task has exactly one attached BSW extension, we have . In early development stages, however, engineers typically lack a reliable model of the final global BSW task set , yet feasibility decisions must already be made.
A finer model could distinguish individual RTE calls, sender–receiver labels, and inter-task communication paths. We deliberately use the coarser task-composition proxy because these details are often unavailable in the early architectural phase targeted here, whereas the number of runnable instances per task frame is already determined by clustering.
Second, global BSW tasks represent periodic platform services that are scheduled independently of application tasks, such as OS, RTE, communication stacks, and diagnostics. In early development stages, the final set of such tasks is often not yet available, although feasibility decisions must already reserve timing and memory capacity for them. Eq. 13 therefore estimates only the number of global BSW tasks used in this early-phase abstraction. It is an empirical surrogate that enables integrated timing/memory analysis despite missing information based on empirical data. For our evaluation, we calibrated it from the abstracted case-study profile, not a schedulability theorem and not a consequence of the utilization bound used below. Once the concrete BSW task set is available, Eq. 13 is replaced by the actual task set and only the feasibility checks in Equations 14 and 15 remain.
| (13) |
How it is used.
The estimate in Eq. 13 partitions an unavailable final BSW configuration into two modeled early-phase channels. Task-local extensions reserve BSW work that scales with the constructed application tasks; global BSW tasks reserve separate periodic platform services. These channels are not functionally interchangeable. Rather, the surrogate prevents the early model from double-counting BSW load: if task-local extensions already reserve part of the BSW utilization, the remaining global-BSW estimate is reduced accordingly. The parameters of the generated global BSW tasks – periods, WCETs, SIL labels, and memory envelopes – are then sampled from the global BSW profile summarized in Section 5.1.
Eq. 13 determines the size of the generated global BSW task set. Its utilization is constrained separately. To avoid unrealistically large BSW load, we bound the combined task-local and global BSW utilization using the multiprocessor utilization bound of López et al. [36]. For a platform with cores and an admissible BSW task-count range, this yields an upper BSW-utilization envelope . We require:
| (14) |
Equation 14 states that the utilization of global BSW tasks must fit into the remaining BSW envelope after reserving the utilization already accounted for by task-local extensions.
Finally, BSW also consumes ROM. Let denote the ROM footprint associated with BSW on core (both for global BSW tasks in and task-local BSW extensions), and the per-core ROM capacity available to software. We require:
| (15) |
This constraint ensures that the BSW memory footprint remains below the available per-core ROM budget, leaving sufficient space for application tasks . The combined utilization and memory constraints for BSW and application tasks are enforced during allocation and schedulability analysis in Section 4.6, where the overall task set is mapped to the multicore platform .
4.5 Composing Coherent Task Groups
The next step prepares for core allocation by identifying sets of tasks that must be co-located. After the merging procedure in Section 4.3, some job-level dependencies (JLDs) become internal to individual tasks, while others remain between tasks. The latter form the reduced set of task-level JLDs . In addition, SW-C boundaries impose further co-location requirements: all tasks that contain cyclic runnables of the same SW-C must reside on the same core to respect the SW-C’s memory footprint and SIL context.
We capture these constraints by grouping tasks into coherent task groups , where all tasks inside a group must be allocated to the same core. First, each task-level JLD induces a grouping constraint: for any abstracted JLD , the two tasks must be placed in the same group,
| (16) |
In practice, an empty set is populated iteratively: when a JLD connects two tasks, a new group is created (or existing groups are merged) such that both tasks end up in the same .
Second, we must respect the structure of software components. For each SW-C , consider its cyclic runnables. These runnables may be mapped either to the same task or to different tasks after merging. All tasks containing cyclic runnables of the same SW-C must, however, be assigned to the same task group to ensure that the SW-C’s ROM/RAM footprint is allocated consistently on a single core and to preserve its SIL context. Let denote the task containing runnable , and let denote the task group containing task . We then require
| (17) |
In other words, no SW-C may be split across different groups: if two tasks contain cyclic runnables from the same SW-C, they must belong to the same . Existing groups are extended accordingly, or new groups are created when needed.
After processing all JLDs and SW-Cs, we obtain: (a) a set of coherent task groups , each of which must be mapped to a single core, and (b) a remaining set of independent tasks , defined as the tasks not contained in any group, .
In the subsequent allocation step (Section 4.6), each task group in and each individual task in is treated as an indivisible unit that must be placed on exactly one core in , while satisfying both schedulability and memory constraints.
4.6 Orchestrating Task Abstraction, Mapping and Scheduling
This final step brings together the previous phases. As a result of runnable merging, multiframe application tasks are represented by periodic abstractions. Some precedence constraints may still remain between application tasks if they could not be resolved internally during merging; these constitute the reduced task-level JLD set .
Similarly, we represent the global share of basic software by periodic BSW tasks . Hence, at this stage both application and global BSW tasks are abstracted and treated uniformly for scheduling, i. e., .
For memory allocation, however, we must distinguish between the two types: global BSW contributes a pre-accounted per-core ROM envelope (Eq. 15), whereas application memory costs arise from the software components (SW-Cs) containing the mapped runnables. In particular, all tasks containing runnables of a given SW-C must be mapped to the same core, as enforced by the task-group construction in Section 4.5.
To test schedulability under JLD constraints, we adopt the approach of Forget et al. [23]: for the set of tasks mapped to a given core, we synthesize offsets and deadlines that satisfy the extended precedences and then assign fixed priorities (via a modified Audsley-style procedure) such that the resulting task set is schedulable. We use partitioned scheduling and apply this per core; by construction of (Section 4.5), all tasks connected by task-level JLDs are co-located on the same core.
Orchestration loop.
We treat each task group as an indivisible unit, map groups first (worst-fit by utilization), and then place remaining tasks in . After each placement, we (i) run the per-core schedulability test described above and (ii) check per-core ROM/RAM feasibility and the BSW ROM envelope. If a placement causes infeasibility, we backtrack locally by selecting the next-best core (worst-fit order) for the affected unit.
Let denote the set of runnables mapped to core after allocation, and let be the induced set of SW-Cs placed on core . Memory feasibility is then checked per core as
| (18) |
This accounts for the ROM/RAM footprint of a SW-C’s runnables assigned to a core.
Assuming that all timing used by our analysis are sound upper bounds (i. e., include any potentially unmodeled interference) mapping accepted by our orchestration satisfies: (i) data-age constraints; (ii) SIL separation as modeled; (iii) ROM/RAM and (iv) BSW accounting by construction of extensions and enforcement of the utilization/ROM envelopes.
5 Evaluation
Our primary goal is to quantify the practical impact of treating SIL constraints, BSW costs, and memory as first-class citizens. Thus, we investigated how progressively richer modeling and clustering decisions affect feasibility margins and resource efficiency. In addition, we included an ablation that transitions from conservative budgets to WCETs to assess how much of the resulting clustering and mapping structure is retained in refinement.
Note that a direct comparison against external baselines was not straightforward for two reasons. First, most related allocation and precedence-aware scheduling approaches assume that the task decomposition is given and therefore do not cover the coupled design space we target: SIL-constrained runnable clustering and multirate task construction together with explicit modeling of task-local BSW extensions and global BSW tasks. Second, there are currently no readily available public benchmarks that reflect automotive systems at our granularity – particularly in distinguishing BSW extensions from global BSW tasks and enforcing SIL constraints at the component/runnable level. This benchmark gap is the motivation for our case study and the derived system generator used throughout this evaluation. We therefore compare against progressively less informed variants of our own flow to isolate the contribution of individual modeling and optimization steps.
5.1 Industrial Case Study
Our evaluation is grounded in an abstracted profile of a production-grade automotive motion/drive controller [15]. Due to IP restrictions, we cannot disclose the original architecture, functionality, or exact per-task timing values. Instead, the companion case study extracts correlation-preserving ranges and distributions for the properties that affect our optimization problem: SIL composition, runnable timing, cause-effect-chain structure, task-local BSW extensions, global BSW services, and memory envelopes. The following profile parameters are used directly by our benchmark generator; similar to TASKers [18], the generator constructs instances under multiple interacting structural and timing constraints.
- Application structure and SIL mix.
-
Software components (SW-Cs) are the architectural containers that carry SIL labels and memory footprints; their runnables inherit the corresponding SIL. The abstracted SIL distribution is QM/ASIL A/B/C/D = /// /. SIL-specific memory ranges span ROM and RAM. The SW-C profile has a correlation factor of 0.5174 with the industrial baseline.
- Runnable timing.
-
Cyclic runnables use automotive periods from to . The dominant application periods are () and (); additional mass appears at () and (). Period-specific timing budgets range from to ; the runnable timing profile has a correlation factor of 0.4322 with the baseline.
- Cause-effect chains.
-
Chains contain one to three activation patterns and between 2 and 18 runnables. Their data-age bounds are specified relative to the chain hyperperiod, with factors between 1.8 and 4.9. Runnables may occur in multiple chains, which is why the generator must preserve chain context when constructing SIL-compatible clusters.
- Task-local BSW extensions.
-
Task-local BSW work models services attached to application-task activations, such as RTE and communication handling. The case study shows that this overhead depends strongly on the number of runnable instances in a task frame. The abstracted BSW ratio decreases with task size: for single-runnable frames, for two runnables, for three runnables, and for frames with at least six runnables. The corresponding correlation factor is 0.5042.
- Global BSW tasks.
-
Separate periodic BSW tasks model global platform services such as OS, RTE, communication stacks, and diagnostics. Their periods range from to , with dominant shares at () and (); period-specific budgets range from to . The global BSW task profile has a correlation factor of 0.4189. The underlying industrial BSW set contains approximately system-related BSW runnables, with up to 200 runnables per BSW task.
- BSW memory envelope.
-
Global BSW memory is accounted for separately from application memory. The abstracted per-core BSW ROM reservation ranges from to and reduces the ROM capacity available for application SW-Cs on that core.
The synthesized benchmarks should therefore be read as application slices sampled from this industrial profile, not as complete replicas of the deployed ECU. This distinction is important for interpreting the scale of the experiments: the generated instances vary the number of application runnables to obtain many independent optimization problems, whereas the task-local and global BSW abstractions remain anchored in the system-wide BSW profile. Table 2 details those numbers further.
| Property | Abstracted values used in synthesis |
|---|---|
| SIL distribution | QM: 41 %; ASIL A: 7 %; ASIL B: 14 %; ASIL C: 10 %; ASIL D: 28 % |
| SW-C memory | ROM: 6–255 kB; RAM: 0.5–29 kB; sampled by SIL class |
| Runnable periods | 1, 5, 10, 20, 50, 100, 200, 500, 1000 ms |
| Dominant app. periods | 5 ms: 31 %; 10 ms: 25 %; 20 ms: 12 %; 100 ms: 10 % |
| Fast runnable budgets | 1 ms: 15–290 s; 5 ms: 10–725 s; 10 ms: 22–1218 s |
| Slow runnable budgets | 100 ms: 228–2447 s; 500 ms: 403–6176 s; 1000 ms: 1209–9200 s |
| Cause-effect chains | 1–3 activation patterns; 2–18 runnables per chain; age bound: 1.8–4.9 hyperp. |
| Task-local BSW ext. | 1 runnable: 24–57 %; 2: 19–48 %; 3: 15–39 %; 6: 8–14 % |
| Global BSW periods | 1, 2, 5, 10, 20, 50, 100, 200 ms |
| Dominant BSW periods | 5 ms: 31 %; 10 ms: 34 % |
| Global BSW budgets | 14–1698 s over all BSW periods; period-specific ranges used for sampling |
| BSW memory envelope | 634–1258 kB ROM reserved per lockstep core |
| BSW system scale | approx. 6000 system-related BSW runnables; up to 200 runnables per BSW task |
5.2 Experimental Setup
Benchmark synthesis.
Based on the case-study profile [15], we implemented the system and task set generator Driverator [14]. A random seed, an application-size parameter, and a configuration variant identify each generated instance. The application-size parameter controls the number of generated application runnables (); these instances are application slices sampled from the industrial profile, not complete replicas of the deployed ECU. The much larger figure of approximately runnables refers to the system-wide BSW profile from which global BSW task parameters are derived.
For each seed and size, Driverator first samples SW-Cs, assigns SIL labels, and draws SIL-specific ROM/RAM footprints. It then creates cyclic application runnables, binds them to SW-Cs so that runnables inherit the SW-C SIL, and samples periods and timing budgets from the period-specific case-study ranges. Next, it constructs cause-effect chains by sampling the number of activation patterns, the number of runnables per chain, and the corresponding data-age bound. Finally, it derives task-local BSW extension factors from the task-composition profile and generates global BSW tasks from the global BSW profile. The resulting base instance is then analyzed under the configuration variants in Table 3.
Filtering and counted instances.
We distinguish three outcomes. A generated instance is attempted if the generator produced a complete application/BSW model for a given seed and size. It is schedulable if the corresponding variant can construct tasks, derive JLD-compatible timing constraints, and pass the schedulability test. It is allocatable if, in addition, the resulting task set can be mapped to cores while satisfying the SIL and memory constraints enabled for that variant. Thus, the columns Sched. Systems and Allocatable in Table 3 report post-analysis outcomes, not independent benchmark pools. Since each configuration variant enables different constraints, the counts are intentionally variant-specific. The total row summarizes the number of completed analyses across all variants; it should not be interpreted as the number of distinct generated base systems.
Platform model and implementation.
As a representative allocation target, we selected the AURIX TC39x family: six cores, with four lockstep cores serving high-SIL workloads and dedicated RAM. We excluded the two performance cores as they may not run SIL runnables. We did not model interference and assumed it to be either prevented by platform configuration or covered by conservative WCETs. We assumed partitioned, preemptive fixed-priority scheduling (Section 3). All experiments ran on a 64-core AMD CPU at 3.1 GHz with 384 GB RAM; IBM CPLEX Optimizer 22.1.1 solves the CP model in Section 4.3.
Configuration variants.
To expose the effect of modeling choices and clustering decisions, we evaluated five configuration variants (Table 3, Figures 5 and 5). The column Basic Software distinguishes whether a variant accounts only for task-local BSW extensions (Exts), only for periodic global BSW tasks (Tasks), or for both (Both). Variants ① and ② are diagnostic, requirement-incomplete boundary cases: they deliberately combine BSW-channel selection with simplified constraint settings and are therefore not clean single-factor ablations. We retain them to show, in compact form, how partial BSW accounting and omitted constraints affect the resulting utilization. Variants ③–⑤ form the feasible comparison set: they enable both data-age and SIL constraints and progressively introduce clustering/merging under full BSW accounting. The additional BSW reference \scriptsizeB⃝ in Figure 4(c) is not a configuration variant; it disables SIL and data-age constraints only to expose the complete BSW approximation, that is the split between task-local extensions and global BSW tasks on budgets.
- ① NoJLD+BSWTasks (non-compliant).
-
We disabled data-age constraints (no JLDs / no age bounds) while keeping SIL constraints enabled. Application runnables remained unmerged (one runnable per task), and we accounted only for global BSW tasks while omitting task-local BSW extensions. This variant is a diagnostic boundary case, not a feasible architecture: it combines missing chain semantics with global-only BSW accounting. It is included to show the scale of global BSW tasks within a conservative, unmerged task structure and to provide a lower-dimensional reference for later full-accounting variants.
- ② NoSIL+BSWExts (non-compliant).
-
We disabled SIL constraints while keeping data-age constraints enabled and allowing task merging. We accounted only for task-local BSW extensions while omitting global BSW tasks. This variant is again a diagnostic boundary case, not a feasible architecture: it combines missing safety partitioning with local-only BSW accounting. It is included to show how JLD-constrained task construction interacts with task-local BSW extensions when SIL-induced splitting is removed.
- ③ NoCluster+BSWFull (baseline).
-
We enabled both data-age and SIL constraints and account for both BSW extensions and global BSW tasks. Runnables remain unmerged (one runnable per task). This establishes a feasible baseline with full BSW accounting, against which merging/clustering decisions are evaluated.
- ④ SeqCluster+BSWFull.
-
Starting from ③, we enabled JLD-constrained task merging (data-age aware) under SIL constraints and full BSW accounting. Within each chain, consecutive runnables sharing the same SIL are clustered, preserving the original runnable order; runnables shared across chains are treated separately. This captures the first stage of reducing pessimism through merging while preserving chain semantics.
- ⑤ SILCluster+BSWFull.
Table 3 summarizes the evaluation scale and runtimes. Across all variant-specific analyses, runs produced schedulable task sets and of those also satisfied the enabled memory-allocation constraints. The table also lists which constraints were enforced (data age / SIL / task merging) and which BSW accounting mode was used.
| Configuration Variant | Sched. Systems | Alloc. Systems | Data Age | SIL | Task Merging | Basic Software | Analysis Time |
| ① NoJLD+BSWTasks1111 (non-compl.) | 3,386 | 3,248 | No | Yes | No | Tasks | [1 s, 1.4 h] |
| ② NoSIL+BSWExts2222 (non-compl.) | 2,477 | 2,212 | Yes | No | Yes | Exts | [1 s, 1.2 h] |
| ③ NoCluster+BSWFull (Baseline) | 2,865 | 2,701 | Yes | Yes | No | Both | [2 s, 2.1 h] |
| ④ SeqCluster+BSWFull | 2,594 | 2,449 | Yes | Yes | Yes | Both | [1 s, 2.7 h] |
| ⑤ SILCluster+BSWFull | 2,503 | 2,363 | Yes | Yes | Yes | Both | [1 s, 2.9 h] |
| Total | 13,825 | 12,973 | – | – | – | – | [1 s, 2.9 h] |
| 1111 Only global BSW tasks are considered. 2222 Only task-local BSW extensions are considered. | |||||||
5.3 Feasibility, Efficiency, and Practical Impact
The following results were obtained from synthesized systems produced by our generator, using budgets only. Global BSW tasks were estimated via Eq. 13 and constrained by Eqs. 14–15. The Reality Check applies the full approach to the industrial controller configuration.
Analysis Overhead.
Across all variants and synthesized systems, end-to-end runtimes range from 1 s to 2.9 h and vary substantially with system structure (and thus analyzability), yet remain within a practical range for iterative engineering workflows. The dominant costs stem from application task construction (CP-based multiframe configuration) and the subsequent timing analysis; other steps contribute only minor overhead in comparison.
From Constraints to Reduced Pessimism.
Our initial claim was that explicit BSW modeling and SIL/JLD-aware clustering reduce analysis pessimism and increase feasibility margins. How to read the plots: The absolute utilizations in Figures 5 and 5 are informative but dense. Variants ① and ② are diagnostic boundary cases, whereas ③–⑤ form the feasible full-accounting comparison set. The normalized ratios in Figure 6 provide the clearest view of relative gains and should be consulted alongside the absolute plots.
Global BSW tasks are a dominant driver: Variant ① combines global-only BSW accounting with disabled data-age enforcement and unmerged application tasks. In this diagnostic setting, global BSW tasks account for about 42 % utilization on average, with utilization increasing quickly as system size grows. This does not constitute a clean single-factor ablation, but it shows that global BSW is a first-order design concern. Since ① disables JLDs, it violates chain semantics by construction and serves only as a non-compliant diagnostic reference.
Task-local BSW extensions equally matter, but depend on runnable mapping: Variant ② quantifies task-local BSW extensions under JLD-enforced data age and merging, but it omits global BSW tasks and disables SIL constraints. Hence, its absolute utilization is not directly comparable to full-accounting variants; one must conceptually add the missing global BSW share exposed by ①. Nevertheless, ② shows that extensions remain non-negligible and that enforcing data-age constraints contributes substantially to overall utilization. The variant violates safety partitioning by construction and is included only as a non-compliant diagnostic boundary case.
Our BSW approximation remains bounded: Since ① and ② expose only one BSW channel each, Figure 4(c) reports the unconstrained BSW reference \scriptsizeB⃝. It shows the complete generated BSW utilization, split into task-local extensions and global BSW tasks. The combined BSW utilization stays below the Lopez upper-utilization envelope by construction: Eq. 14 first reserves the task-local contribution and then restricts global BSW tasks to the residual budget . Thus, \scriptsizeB⃝ does not independently validate the bound but makes the calibration of the early-phase BSW model transparent.
Full constraints and full BSW accounting increase pessimism: Variant ③ enables both SIL and data-age constraints and accounts for both BSW types, but keeps runnables one-per-task (no clustering). This represents a feasible yet pessimistic baseline and yields the highest total utilization among the feasible variants; the disproportionate growth in BSW utilization is most clearly visible in Figure 6(b).
SIL/BSW-aware clustering progressively reduces pessimism: Variants ④ (SeqCluster+ BSWFull) and ⑤ (SILCluster+BSWFull) progressively reduce pessimism by clustering/merging under full constraints and full BSW accounting. Figure 6 shows a monotone reduction in both total and BSW utilization from ③ to ④ to ⑤, with improvements becoming more pronounced as system size grows. Notably, the full approach (⑤) can achieve utilization below the diagnostic configurations that ignore either JLDs (①) or SIL constraints / global BSW tasks (②), indicating that the gains stem from improved task construction under realistic constraints rather than from relaxing the constraint set.
From this set of experiments, we conclude that BSW is a primary utilization driver and must be modeled explicitly; within that realistic setting, our SIL/BSW-aware clustering effectively reduces pessimism and recovers feasibility margins.
Data Age Impact.
As a sanity check against established cause-effect chain analysis practice, Figure 7 plots, for each cause-effect chain, the ratio of computed end-to-end latency to its data-age bound (ratios satisfy the constraint). In ① (NoJLD+BSWTasks), latencies are evaluated without enforcing JLDs; only about half of the chains meet their bounds, confirming that ① violates data-age requirements by construction and thus serves only as a diagnostic extreme. In contrast, all variants that enable JLDs (②–⑤) satisfy the data-age bounds by construction; we illustrate this with the feasible baseline ③ (NoCluster+BSWFull) in Figure 7. This confirms that our implementation of JLD-based enforcement behaves as expected, and that the utilization results discussed above are obtained under data-age compliant configurations.
Allocation and Memory Consumption.
We propose that feasibility-relevant memory constraints must be considered alongside timing. Therefore, our experiments in Figure 8 report cumulative ROM/RAM footprints induced by SW-Cs, where each SW-C aggregates the budgets of its constituent runnables. We compared a default SW-C partitioning (one cyclic runnable per SW-C) against an extended partitioning (fewer SW-Cs hosting up to two runnables each), which improved memory efficiency by reducing per-component overheads. As the number and size of SW-Cs grew, both schemes approached the per-core resource limits of the target platform (Section 5.2). Global BSW memory was accounted for separately via the per-core envelope in Eq. 15. We reason that even when clustering reduces utilization, memory remains critical and must be enforced jointly with schedulability.
Reality Check.
To assess practical effectiveness, we applied our full approach (⑤ SILCluster+BSWFull) to our real-world motion and drive controller in its early-design configuration (all constraints enabled). The end-to-end analysis completed in 2.43 h and produced a feasible mapping that respects SIL separation, data-age constraints, and per-core memory limits.
We report results as ratios normalized to the controller’s deployed configuration (deployed baseline = 1.0). In terms of utilization, our approach reduces total CPU load to 0.9325 (7 % improvement) and BSW utilization to 0.9278 (7 % improvement), indicating that SIL-aware clustering together with explicit BSW modeling can translate into tangible headroom in real-world development cycles. This check does not validate Eq. 13 as a universal model, but it confirms that the early-phase BSW abstraction yields a total BSW load in the same range as the deployed industrial configuration. In terms of memory, all cores remain close to capacity; ROM improves slightly to 0.9893, while RAM remains essentially unchanged at 0.9954. The framework yields meaningful utilization gains on a highly loaded production-grade automotive system, suggesting that it can provide actionable guidance when revisiting architectures across iterative integration and update cycles.
5.4 Stability and Architectural Churn
We assess how much of the structural allocation produced by our SIL/BSW-aware flow is retained when execution-time inputs are refined from early budgets toward WCETs.
Stability indicators.
We quantify architectural churn using overlap-based stability scores (not a metric in the strict mathematical sense). A score of 1 means that the same tasks remain co-located on equivalent cores; a score of 0 means that no such co-location structure is retained. The underlying engineering notion is that the costly decision is the co-location structure of periodic tasks; reordering within a core (priorities) or swapping equivalent lockstep cores is comparatively cheap. Accordingly, we measure how well the original per-core task grouping is preserved. Let denote the full periodic task set (application multiframe tasks and global BSW tasks), and let be the set of lockstep cores. For a reference solution (at the initial budget stage), let be the set of tasks allocated to core ; after refinement, let denote the corresponding set. We first compute a directional fixed-label retention score , which answers: how much of the initial allocation is retained on the same labeled core? Since lockstep cores are interchangeable in our model, we additionally allow a relabeling of cores and compute the best matching between the per-core task sets: , where ranges over permutations of the lockstep cores. In practice, we keep any unchanged cores with fixed (they contribute a value of in the average) and solve the remaining assignment as a maximum-overlap matching.
We report overall stability as and define churn as . Thus, we do not penalize priority changes or core label swaps, but we do penalize changes in the co-located task sets that drive integration/configuration effort.
Refinement experiment.
For each synthesized system, we start from conservative execution-time budgets (as in the previous experiments) and compute a reference allocation. We then progressively replace budget values by WCET samples for increasing fractions of execution-time parameters: , and (budgets WCETs), and re-run the toolchain to obtain a refined allocation. Importantly, for each refinement level we re-sample which parameters are switched independently (e.g., the subset is not necessarily contained in the subset). This yields a deliberately conservative estimate of stability: unlike a realistic iterative workflow where measured values accumulate over time, our setup injects additional variation and thus tends to maximize observed churn.
Results.
Figure 9 reports stability distributions over several thousand generated systems for variants ① and ③–⑤. Across all refinement levels, the feasible variants with full BSW accounting and clustering (③–⑤) consistently achieve higher stability than the diagnostic variant ①. In particular, ⑤ (SILCluster+BSWFull) shows the highest median stability and the tightest spread, indicating that SIL/BSW-aware clustering reduces the need for structural remapping as timing inputs change. Compared to ①, stability improves by roughly 20–30 percentage points (depending on refinement level), despite the conservative re-sampling.
Figure 10 complements this view by reporting normalized total utilization for the same refinement experiment. Values below 1 indicate that early budgets were conservative and that refining toward WCETs reduces execution-time pessimism; conversely, higher values imply less headroom. Variants ③–⑤ exhibit lower normalized utilization than ①, with ⑤ lowest overall. This additional headroom helps absorb timing refinements without forcing structural changes, which is consistent with the stability trends in Figure 9.
Taken together, these results support using our toolchain as a recurring architectural analysis step during budget-to-WCET refinement. The full SIL/BSW-aware variant does not eliminate architectural churn, but it consistently retains more of the initial co-location structure than less-informed variants even under aggressive resampling. We therefore interpret the stability experiment as evidence for the relative robustness of the structural decisions.
The absolute stability values should not be read as evidence that architectural churn disappears. Values around 0.5–0.6 still indicate substantial structural change under aggressive changes – we expect better results in actual use, since measured WCET information typically accumulates monotonically rather than being re-replaced by budgets. We therefore use the experiment primarily as a relative robustness test: under identical refinement and resampling conditions, SIL/BSW-aware clustering retains more of the initial co-location structure than less-informed variants.
6 Discussion and Conclusion
We presented a chain-aware analysis and optimization flow for automotive ECUs that treats SIL constraints, Basic Software (BSW) costs (task-local extensions and global BSW tasks), and memory as first-class citizens. Grounded in a real-world motion and drive controller, our case study revealed that SIL constraints and BSW overheads are tightly coupled to structural architectural decisions (task construction, clustering, and core allocation) and can dominate feasibility margins. Based on these empirical profiles, we derived a system generator and implemented a heuristic toolchain that combines SIL-aware clustering, multirate task construction, and BSW- and memory-aware multicore allocation, with feasibility checks under precedence constraints.
Our evaluation demonstrates three key takeaways. First, explicit BSW accounting is essential: both global BSW tasks and task-local extensions materially influence utilization and thus feasibility margins, and treating BSW merely as a fixed margin can be misleading. Second, SIL/JLD-aware clustering reduces pessimism in analysis under full constraint sets, recovering substantial headroom compared to unclustered baselines. Third, beyond single-shot feasibility, our toolchain can be used repeatedly as timing information is refined: in the industrial configuration, our approach yields a utilization reduction, and our refinement study (budgets WCETs) shows that the full SIL/BSW-aware variant preserves more of the initial co-location structure than less informed variants. Taken together, these results support using the approach not only for early architectural exploration, but also as a recurring decision-support step in iterative SDV development when timing parameters evolve more frequently than safety- and BSW-relevant architectural structure.
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