DARTS.9.2.4.pdf
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Document
Wiring Circuits Is Easy as {0, 1, ω}, or Is It... (Artifact)
Authors
Jan de Muijnck-Hughes 
,
Wim Vanderbauwhede
-
Part of:
Issue:
Special Issue of the 37th European Conference on Object-Oriented Programming (ECOOP 2023)
Volume: DARTS, Volume 9 (ECOOP 2023)
Conference: European Conference on Object-Oriented Programming (ECOOP)
Journal: Dagstuhl Artifacts Series (DARTS) - License:
Creative Commons Attribution 4.0 International license
- Publication Date: 2023-07-11
Artifact Description
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Cite AsGet BibTex
Jan de Muijnck-Hughes and Wim Vanderbauwhede. Wiring Circuits Is Easy as {0, 1, ω}, or Is It... (Artifact). In Special Issue of the 37th European Conference on Object-Oriented Programming (ECOOP 2023). Dagstuhl Artifacts Series (DARTS), Volume 9, Issue 2, pp. 4:1-4:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
https://doi.org/10.4230/DARTS.9.2.4
https://doi.org/10.4230/DARTS.9.2.4
Artifact
DARTS-9-2-4-artifact-48ffa350d41ecebf1c25e7936a319797.tar.gz
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Artifact Evaluation Policy
The artifact has been evaluated as described in the ECOOP 2023 Call for Artifacts and the ACM Artifact Review and Badging Policy
Abstract
We present two proof-of-concept languages (Circuits & CirQTS) that showcases how fancy types (namely linear & dependent types) can enrich hardware design tooling such that we can move existing external static analysis checks into the language’s type-system. Using our approach will lead to the enhanced safety of designs, and increase in design productivity, through early identification and reduction of connection errors.
This artefact presents our verified implementations (as realised in Idris2) of the simply (Circuits) and fancily typed (CirQTS) languages, and the test suite used to assess efficacy of our approach.
Subject Classification
ACM Subject Classification
- Software and its engineering → General programming languages
- Software and its engineering → Language features
- Software and its engineering → Domain specific languages
- Software and its engineering → System modeling languages
Keywords
- Hardware Design
- Linear Types
- Dependent Types
- DSLs
- Idris
- SystemVerilog
- Netlists
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