Towards Dilated Placement of Dynamic NoC Cores

Abstract

Instead of mapping application task graphs in a compact manner onto
reconfigurable devices using a network-on-chip for interconnecting
application cores, we propose dilating the mappings as much as the
available latencies on critical connections allow. In a dilated mapping,
the unused resources between an application's configured components can
be used to provide additional flexibility when the configuration needs
to change. We motivate the reasons for dilating application task graphs
targeted at reconfigurable devices; derive a simulated annealing approach
to dilating the placement of such graphs; and present preliminary results
of applying the algorithm to synthetic test cases. The method appears to
result in successful and meaningful graph dilation and could be further
tuned to satisfy desired power constraints.